Lower Power 71V256SA 3.3V CMOS Fast SRAM 256K (32K x 8-Bit) Features Description Ideal for high-performance processor secondary cache The IDT71V256SA is a 262,144-bit high-speed static RAM organized Commercial (0C to +70C) and Industrial (40C to +85C) as 32K x 8. It is fabricated using a high-performance, high-reliability CMOS temperature range options technology. Fast access times: The IDT71V256SA has outstanding low power characteristics while Commercial and Industrial: 12/15/20ns at the same time maintaining very high performance. Address access Low standby current (maximum): times of as fast as 12ns are ideal for 3.3V secondary cache in 3.3V 2mA full standby desktop designs. Small packages for space-efficient layouts: When power management logic puts the IDT71V256SA in standby 28-pin 300 mil SOJ mode, its very low power characteristics contribute to extended battery life. 28-pin TSOP Type I By taking CS HIGH, the SRAM will automatically go to a low power standby Produced with advanced high-performance CMOS mode and will remain in standby as long as CS remains HIGH. Further- technology more, under full standby mode (CS at CMOS level, f=0), power consump- Inputs and outputs are LVTTL-compatible tion is guaranteed to always be less than 6.6mW and typically will be much Single 3.3V(0.3V) power supply smaller. Industrial temperature range (40C to +85C) is available The IDT71V256SA is packaged in a 28-pin 300 mil SOJ and a 28-pin for selected speeds 300 mil TSOP Type I. Green parts available, see ordering information Functional Block Diagram A0 VCC GND 262,144 BIT ADDRESS MEMORY ARRAY DECODER A14 I/O0 I/O CONTROL INPUT DATA CIRCUIT I/O7 , CS CONTROL OE CIRCUIT 3101 drw 01 WE 1 Jun.02.2071V256SA 3.3V CMOS Static RAM 256K (32K x 8-Bit) Commercial and Industrial Temperature Ranges (1) (1) Pin Configurations Truth Table WE CS OE I/O Function A14 1 28 VCC X H X High-Z Standby (ISB) 27 A12 2 WE A 7 3 26 A13 XVHC X High-Z Standby (ISB1) 4 25 A 6 A 8 A 5 5 24 A 9 H L H High-Z Output Disable 71V256SA 6 23 A 4 A11 PJ G28 HL L DOUT Read A 3 7 22 OE 8 21 A10 A 2 LL X DIN Write 9 20 CS A 1 10 19 A 0 I/O7 3101 tbl 02 NOTE: I/O0 11 18 I/O6 1. H = VIH, L = VIL, X = Dont Care I/O1 12 17 I/O5 16 I/O2 13 I/O4 (1) Absolute Maximum Ratings 14 15 GND I/O3 Symbol Rating Com l Unit 3101 drw 02 VCC Supply Voltage -0.5 to +4.6 V DIP/SOJ Relative to GND Top View (2) VTERM Terminal Voltage -0.5 to VCC+0.5 V Relative to GND o TBIAS Temperature Under Bias -55 to +125 C 22 21 A10 OE o 23 20 CS TSTG Storage Temperature -55 to +125 C A11 24 19 I/O7 A9 25 18 PT Power Dissipation 1.0 W A8 I/O6 A13 26 17 I/O5 27 16 WE I/O4 IOUT DC Output Current 50 mA 71V256SA 15 VCC 28 I/O3 PZG28 3101 tbl 03 A14 1 14 GND 2 13 A12 I/O2 NOTES: A7 3 12 I/O1 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS 11 A6 4 I/O0 may cause permanent damage to the device. This is a stress rating only and A5 5 10 A0 functional operation of the device at these or any other conditions above those 6 9 A4 A1 indicated in the operational sections of this specification is not implied. Exposure A3 7 8 A2 to absolute maximum rating conditions for extended periods may affect 3101 drw 03 reliability. 2. Input, Output, and I/O terminals 4.6V maximum. TSOP Top View NOTE: Capacitance 1. This text does not indicate orientation of actual part-marking. (TA = +25C, f = 1.0MHz, SOJ package) (1) Symbol Parameter Conditions Max. Unit CIN Input Capacitance VIN = 3dV 6 pF Pin Descriptions COUT Output Capacitance VOUT = 3dV 7 pF Name Description 3101 tbl 04 NOTE: A0 - A14 Addresses 1. This parameter is determined by device characterization, but is not production tested. I/O0 - I/O7 Data Input/Output Chip Select CS WE Write Enable Recommended Operating Output Enable OE Temperature and Supply Voltage Grade Temperature GND Vcc GND Ground O O Commercial 0 C to +70 C 0V 3.3V 0.3V VCC Power O O 3101 tbl 01 Industrial -40 C to +85 C 0V 3.3V 0.3V 3101 tbl 05 2 Jun.02.20