71V30S55TFG Renesas

71V30S/L HIGH-SPEED 3.3V 1K X 8 DUAL-PORT STATIC RAM Features High-speed access On-chip port arbitration logic Commercial: 25/55ns (max.) Interrupt flags for port-to-port communication Fully asynchronous operation from either port Industrial 35ns (max.) Battery backup operation, 2V data retention (L Only) Low-power operation TTL-compatible, single 3.3V 0.3V power supply IDT71V30S O O Industrial temperature range (-40 C to +85 C) is available Active: 375mW (typ.) for selected speeds Standby: 5mW (typ.) Green parts available, see ordering information IDT71V30L Active: 375mW (typ.) Standby: 1mW (typ.) Functional Block Diagram OER OEL CER CEL R/WR R/WL I/O0R-I/O7R I/O0L-I/O7L I/O I/O Control Control (1) (1) BUSYL BUSYR A9L A9R Address MEMORY Address Decoder ARRAY Decoder A0R A0L 10 10 ARBITRATION CEL and CER INTERRUPT OEL OER LOGIC R/WR R/WL (2) (2) INTL INTR 3741 drw 01 NOTES: 1. IDT71V30: BUSY outputs are non-tristatable push-pulls. 2. INT outputs are non-tristable push-pull output structure. JUNE 2019 1 DSC 3741/14 2019 Integrated Device Technology, Inc.71V30S/L High-Speed 1K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges Description down feature, controlled by CE, permits the on chip circuitry of each port to enter a very low standby power mode. The IDT71V30 is a high-speed 1K x 8 Dual-Port Static RAM. The Fabricated using CMOS high-performance technology, these de- IDT71V30 is designed to be used as a stand-alone 8-bit Dual-Port vices typically operate on only 375mW of power. Low-power (L) ver- SRAM. sions offer battery backup data retention capability, with each Dual- Both devices provide two independent ports with separate control, Port typically consuming 200W from a 2V battery. address, and I/O pins that permit independent, asynchronous access The IDT71V30 devices are packaged in 64-pin STQFPs. for reads or writes to any location in memory. An automatic power (1,2,3) Pin Configurations 46 454443 424140 393837 363534 48 47 33 49 32 N/C I/O5R 50 31 N/C I/O4R 51 N/C 30 N/C INTR 52 29 I/O3R BUSYR 53 28 I/O2R R/WR 54 27 I/O1R CER 55 26 I/O0R 71V30 VCC (4) GND 56 25 PPG64 VCC 57 24 GND 64-Pin STQFP CEL 58 23 N/C Top View R/WL 59 22 I/O7L BUSYL 60 21 I/O6L 20 INTL 61 I/O5L N/C 62 19 I/O4L 63 N/C 18 N/C 64 17 N/C I/O3L 12 3 4 5 6 7 89 10 11 12 13141516 3741 drw 03 NOTES: 1. All VCC pins must be connected to the power supply. 2. All GND pins must be connected to the ground supply. 3. Package body is approximately 10mm x 10mm x 1.4mm. 4. This package code is used to reference the package diagram. 6.42 2 OE R OEL 0L A A0R A1R A1L 2L A2R A A3R 3L A A A4L 4R A5L A5R A6R A6L N/C N/C A7R 7L A A8R A8L A9R A9L N/C N/C N/C I/O0L I/O7R I/O1L I/O6R I/O2L