HIGH SPEED 3.3V 71V321L 2K X 8 DUAL-PORT STATIC RAM WITH INTERRUPTS Features High-speed access Fully asynchronous operation from either port Commercial & Industrial: 25/35ns (max.) Battery backup operation2V data retention (L only) Low-power operation TTL-compatible, single 3.3V power supply IDT71V321L Available in 52-pin PLCC, 64-pin TQFP and STQFP packages Active: 325mW (typ.) Standby: 1mW (typ.) Industrial temperature range (40C to +85C) is available Two INT flags for port-to-port communications for selected speeds On-chip port arbitration logic (IDT71V321 only) Green parts available, see ordering information BUSY output flag Functional Block Diagram OER OEL CEL CER R/WR R/WL I/O0L-I/O7L I/O0R-I/O7R I/O I/O Control Control (1,2) (1,2) BUSYL BUSYR A10L A10R Address MEMORY Address Decoder ARRAY Decoder A0L A0R 11 11 ARBITRATION and CEL CER INTERRUPT OER OEL LOGIC R/WR R/WL (2) (2) INTR INTL 3026 drw 01 NOTES: 1. IDT71V321 (MASTER): BUSY is an output 2. BUSY and INT are totem-pole outputs. JULY 2019 1 DSC-3026/14 2019 Integrated Device Technology, Inc.71V321L High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges Description The IDT71V321 is a high-speed 2K x 8 Dual-Port Static RAMs port to enter a very low standby power mode. with internal interrupt logic for interprocessor communications. The Fabricated using CMOS high-performance technology, these de- vices typically operate on only 325mW of power. Low-power (L) ver- IDT71V321 is designed to be used as a stand-alone 8-bit Dual-Port sions offer battery backup data retention capability, with each Dual-Port RAM. typically consuming 200W from a 2V battery. The device provides two independent ports with separate control, The IDT71V321 devices are packaged in a 52-pin PLCC, a 64-pin address, and I/O pins that permit independent, asynchronous access TQFP (thin quad flatpack), and a 64-pin STQFP (super thin quad for reads or writes to any location in memory. An automatic power flatpack). down feature, controlled by CE, permits the on chip circuitry of each (1,2,3) Pin Configurations 2019 18 17 16 15 14 13 12 11 10 9 8 I/O 4L 21 7 A 0L 5L 6 I/O 22 OEL I/O 6L 5 A 23 10L 7L 4 I/O 24 INTL 3 NC 25 BUSYL 71V321 2 GND 26 R/WL (4) PLG52 I/O 0R 1 27 CEL 52-Pin PLCC I/O 1R 28 52 V CC Top View I/O 2R 29 51 CER I/O 3R 30 50 R/WR I/O 4R 31 49 BUSYR I/O 5R 32 48 INTR I/O 33 6R 47 A 10R 34 35 36 37 38 39 40 41 42 43 44 45 46 3026 drw 02 46 4544 4342 4140 39 3837 363534 48 47 33 49 32 5R N/C I/O 50 31 N/C I/O4R 51 A10R 30 N/C R 52 INT 29 I/O3R 53 BUSYR 28 I/O2R 54 R/W 27 R I/O1R 71V321 55 R CE 26 I/O0R (4) PPG64 56 CC V 25 GND (4) PNG64 CC 57 V 24 GND 58 64-Pin STQFP CEL 23 N/C 64-Pin TQFP 59 R/W 7L L 22 I/O Top View L 60 BUSY 21 I/O6L 61 INTL 20 5L I/O A10L 62 19 I/O4L NOTES: 63 18 N/C N/C 1. All VCC pins must be connected to power supply. 64 N/C 17 I/O3L 12 3 456 7 89 101112 131415 16 2. All GND pins must be connected to ground supply. 3. J52-1 package body is approximately .75 in x .75 in x .17 in. PP64-1 package body is approximately 10mm x 10mm x 1.4mm. 3026 drw 03 PN64-1 package body is approximately 14mm x 14mm x 1.4mm. 4. This package code is used to reference the package diagram. 6.422 7R I/O I/O 3L NC I/O 2L A 9R 1L I/O A 8R I/O 0L 7R 9L A A 6R A A 8L A 5R A 7L A 4R 6L A A 3R 5L A 4L A 2R A A 1R A 3L A 0R 2L A OER A 1L OER OEL A0L A0R A1R A1L A2R A2L 3R A A3L A4R A4L 5R A5L A A6R A6L N/C N/C A7R A 7L A8R A 8L A9R A9L N/C N/C N/C I/O0L I/O7R I/O1L I/O 6R I/O2L