IDT71V3556S/XS 128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs IDT71V3558S/XS 3.3V I/O, Burst Counter IDT71V3556SA/XSA Pipelined Outputs IDT71V3558SA/XSA Features Description 128K x 36, 256K x 18 memory configurations The IDT71V3556/58 are 3.3V high-speed 4,718,592-bit (4.5 Mega- Supports high performance system speed - 200 MHz (x18) bit) synchronous SRAMS. They are designed to eliminate dead bus (3.2 ns Clock-to-Data Access) cycles when turning the bus around between reads and writes, or TM Supports high performance system speed - 166 MHz (x36) writes and reads. Thus, they have been given the name ZBT , or (3.5 ns Clock-to-Data Access) Zero Bus Turnaround. TM ZBT Feature - No dead cycles between write and read Address and control signals are applied to the SRAM during one cycles clock cycle, and two cycles later the associated data cycle occurs, be Internally synchronized output buffer enable eliminates the it read or write. need to control OE The IDT71V3556/58 contain data I/O, address and control signal Single R/W (READ/WRITE) control pin registers. Output enable is the only asynchronous signal and can be Positive clock-edge triggered address, data, and control used to disable the outputs at any given time. signal registers for fully pipelined applications A Clock Enable (CEN) pin allows operation of the IDT71V3556/58 4-word burst capability (interleaved or linear) to be suspended as long as necessary. All synchronous inputs are Individual byte write (BW1 - BW4) control (May tie active) ignored when (CEN) is high and the internal device registers will hold Three chip enables for simple depth expansion their previous values. 3.3V power supply (5%), 3.3V I/O Supply (VDDQ) There are three chip enable pins (CE1, CE2, CE2) that allow the Optional- Boundary Scan JTAG Interface (IEEE 1149.1 user to deselect the device when desired. If any one of these three are compliant) not asserted when ADV/LD is low, no new memory operation can be Packaged in a JEDEC standard 100-pin plastic thin quad initiated. However, any pending data transfers (reads or writes) will be flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch completed. The data bus will tri-state two cycles after chip is deselected ball grid array (fBGA) or a write is initiated. Pin Description Summary A0-A17 Address Inputs Input Synchronous CE1, CE2, CE2 Chip Enables Input Synchronous Output Enable Input Asynchronous OE R/W Read/Write Signal Input Synchronous Clock Enable Input Synchronous CEN Individual Byte Write Selects Input Synchronous BW1, BW2, BW3, BW4 CLK Clock Input N/A ADV/LD Advance burst address / Load new address Input Synchronous Linear / Interleaved Burst Order Input Static LBO TMS Test Mode Select Input Synchronous TDI Test Data Input Input Synchronous TCK Test Clock Input N/A TDO Test Data Output Output Synchronous JTAG Reset (Optional) Input Asynchronous TRST ZZ Sleep Mode Input Synchronous I/O0-I/O31, I/OP1-I/OP4 Data Input / Output I/O Synchronous VDD, VDDQ Core Power, I/O Power Supply Static VSS Ground Supply Static 5281 tbl 01 OCTOBER 2010 1 DSC-5281/11 2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges Description continued The IDT71V3556/58 has an on-chip burst counter. In the burst external address (ADV/LD = LOW) or increment the internal burst mode, the IDT71V3556/58 can provide four cycles of data for a single counter (ADV/LD = HIGH). address presented to the SRAM. The order of the burst sequence is The IDT71V3556/58 SRAMs utilize IDT s latest high-performance defined by the LBO input pin. The LBO pin selects between linear and CMOS process and are packaged in a JEDEC standard 14mm x interleaved burst sequence. The ADV/LD signal is used to load a new 20mm 100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array (BGA) and a 165 fine pitch ball grid array (fBGA). (1) Pin Definition Symbol Pin Function I/O Active Description Synchronous Address inputs. The address register is triggered by a combination of the rising edge of CLK, A0-A17 Address Inputs I N/A ADV/LD low, CEN low, and true chip enables. ADV/LD is a synchronous input that is used to load the internal registers with new address and control when it is sampled low at the rising edge of clock with the chip selected. When ADV/LD is low with the chip ADV/LD Advance / Load I N/A deselected, any burst in progress is terminated. When ADV/LD is sampled high then the internal burst counter is advanced for any burst that was in progress. The external addresses are ignored when ADV/ LD is sampled high. R/W signal is a synchronous input that identifies whether the current load cycle initiated is a Read or Write R/W Read / Write I N/A access to the memory array. The data bus activity for the current cycle takes place two clock cycles later. Synchronous Clock Enable Input. When CEN is sampled high, all other synchronous inputs, including clock are Clock Enable I LOW ignored and outputs remain unchanged. The effect of CEN sampled high on the device outputs is as if the low CEN to high clock transition did not occur. For normal operation, CEN must be sampled low at rising edge of clock. Synchronous byte write enables. Each 9-bit byte has its own active low byte write enable. On load write cycles (When R/W and ADV/LD are sampled low) the appropriate byte write signal (BW1-BW4) must be valid. The byte Individual Byte BW1-BW4 ILOW write signal must also be valid on each cycle of a burst write. Byte Write signals are ignored when R/W is Write Enables sampled high. The appropriate byte(s) of data are written into the device two cycles later. BW1-BW4 can all be tied low if always doing write to the entire 36-bit word. Synchronous active low chip enable. CE1 and CE2 are used with CE2 to enable the IDT71V3556/58. (CE1 or CE1, CE2 Chip Enables I LOW CE2 sampled high or CE2 sampled low) and ADV/LD low at the rising edge of clock, initiates a deselect cycle. TM The ZBT has a two cycle deselect, i.e., the data bus will tri-state two clock cycles after deselect is initiated. Synchronous active high chip enable. CE2 is used with CE1 and CE2 to enable the chip. CE2 has inverted CE2 Chip Enable I HIGH polarity but otherwise identical to CE1 and CE2. This is the clock input to the IDT71V3556/58. Except for OE, all timing references for the device are made with CLK Clock I N/A respect to the rising edge of CLK. I/O0-I/O31 Synchronous data input/output (I/O) pins. Both the data input path and data output path are registered and Data Input/Output I/O N/A I/OP1-I/OP4 triggered by the rising edge of CLK. Burst order selection input. When LBO is high the Interleaved burst sequence is selected. When LBO is low Linear Burst Order I LOW LBO the Linear burst sequence is selected. LBO is a static input and it must not change during device operation. Asynchronous output enable. OE must be low to read data from the 71V3556/58. When OE is high the I/O pins Output Enable I LOW are in a high-impedance state. OE does not need to be actively controlled for read and write cycles. In normal OE operation, OE can be tied low. TMS Test Mode Select I N/A Gives input command for TAP controller. Sampled on rising edge of TDK. This pin has an internal pullup. Serial input of registers placed between TDI and TDO. Sampled on rising edge of TCK. This pin has an internal TDI Test Data Input I N/A pullup. Clock input of TAP controller. Each TAP event is clocked. Test inputs are captured on rising edge of TCK, TCK Test Clock I N/A while test outputs are driven from the falling edge of TCK. This pin has an internal pullup. Serial output of registers placed between TDI and TDO. This output is active depending on the state of the TAP TDO Test Data Output O N/A controller. Optional Asynchronous JTAG reset. Can be used to reset the TAP controller, but not required. JTAG reset JTAG Reset TRST ILOW occurs automatically at power up and also resets using TMS and TCK per IEEE 1149.1. If not used TRST can (Optional) be left floating. This pin has an internal pullup. Only available in BGA package. Synchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down the IDT71V3556/3558 to ZZ Sleep Mode I HIGH its lowest power consumption level. Data retention is guaranteed in Sleep Mode. This pin has an internal pulldown. VDD Power Supply N/A N/A 3.3V core power supply. VDDQ Power Supply N/A N/A 3.3V I/O Supply. VSS Ground N/A N/A Ground. 5281 tbl 02 NOTE: 1. All synchronous inputs must meet specified setup and hold times with respect to CLK. 6.422