128K x 36, 256K x 18, IDT71V3557S 3.3V Synchronous ZBT SRAMs IDT71V3559S 3.3V I/O, Burst Counter, IDT71V3557SA Flow-Through Outputs IDT71V3559SA Features it read or write. 128K x 36, 256K x 18 memory configurations The IDT71V3557/59 contain address, data-in and control signal Supports high performance system speed - 100 MHz registers. The outputs are flow-through (no output data register). Output (7.5 ns Clock-to-Data Access) enable is the only asynchronous signal and can be used to disable the TM ZBT Feature - No dead cycles between write and read outputs at any given time. cycles A Clock Enable (CEN) pin allows operation of the IDT71V3557/59 Internally synchronized output buffer enable eliminates to be suspended as long as necessary. All synchronous inputs are the need to control OE ignored when (CEN) is high and the internal device registers will hold Single R/W (READ/WRITE) control pin their previous values. 4-word burst capability (Interleaved or linear) There are three chip enable pins (CE1, CE2, CE2) that allow the user Individual byte write (BW1 - BW4) control (May tie active) to deselect the device when desired. If any one of these three is not asserted Three chip enables for simple depth expansion when ADV/LD is low, no new memory operation can be 3.3V power supply (5%), 3.3V (5%) I/O Supply (VDDQ) initiated. However, any pending data transfers (reads or writes) will Optional Boundary Scan JTAG Interface (IEEE 1149.1 be completed. The data bus will tri-state one cycle after chip is de- complaint) selected or a write is initiated. Packaged in a JEDEC Standard 100-pin plastic thin quad The IDT71V3557/59 have an on-chip burst counter. In the burst flatpack (TQFP), 119 ball grid array (BGA) and 165 fine mode, the IDT71V3557/59 can provide four cycles of data for a single pitch ball grid array (fBGA) address presented to the SRAM. The order of the burst sequence is Description defined by the LBO input pin. The LBO pin selects between linear and The IDT71V3557/59 are 3.3V high-speed 4,718,592-bit (4.5 Mega- interleaved burst sequence. The ADV/LD signal is used to load a new bit) synchronous SRAMs organized as 128K x 36/256K x 18. They are external address (ADV/LD = LOW) or increment the internal burst counter designed to eliminate dead bus cycles when turning the bus around (ADV/LD = HIGH). between reads and writes, or writes and reads. Thus they have been The IDT71V3557/59 SRAMs utilize IDT s latest high-performance TM given the name ZBT , or Zero Bus Turnaround. CMOS process and are packaged in a JEDEC standard 14mm x 20mm Address and control signals are applied to the SRAM during one clock 100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array cycle, and on the next clock cycle the associated data cycle occurs, be (BGA) and a 165 fine pitch ball grid array (fBGA). Pin Description Summary A0-A17 Address Inputs Input Synchronous Chip Enables Input Synchronous CE1, CE2, CE2 OE Output Enable Input Asynchronous R/W Read/Write Signal Input Synchronous Clock Enable Input Synchronous CEN 1, BW2, BW3, BW4 Individual Byte Write Selects Input Synchronous BW CLK Clock Input N/A ADV/LD Advance burst address / Load new address Input Synchronous LBO Linear / Interleaved Burst Order Input Static TMS Test Mode Select Input Synchronous TDI Test Data Input Input Synchronous TCK Test Clock Input N/A TDO Test Data Output Output Synchronous JTAG Reset (Optional) Input Asynchronous TRST ZZ Sleep Mode Input Synchronous I/O0-I/O31, I/OP1-I/OP4 Data Input / Output I/O Synchronous VDD, VDDQ Core Power, I/O Power Supply Static VSS Ground Supply Static 5282 tbl 01 FEBRUARY 2009 1 2009 Integrated Device Technology, Inc. DSC-5282/09IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with ZBT Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges (1) Pin Definitions Symbol Pin Function I/O Active Description A0-A17 Address Inputs I N/A Synchronous Address inputs. The address register is triggered by a combination of the rising edge of CLK, ADV/LD low, CEN low, and true chip enables. ADV/LD Advance / Load I N/A ADV/LD is a synchronous input that is used to load the internal registers with new address and control when it is sampled low at the rising edge of clock with the chip selected. When ADV/LD is low with the chip deselected, any burst in progress is terminated. When ADV/LD is sampled high then the internal burst counter is advanced for any burst that was in progress. The external addresses are ignored when ADV/ LD is sampled high. R/W Read / Write I N/A R/W signal is a synchronous input that identifies whether the current load cycle initiated is a Read or Write access to the memory array. The data bus activity for the current cycle takes place one clock cycle later. CEN Clock Enable I LOW Synchronous Clock Enable Input. When CEN is sampled high, all other synchronous inputs, including clock are ignored and outputs remain unchanged. The effect of CEN sampled high on the device outputs is as if the low to high clock transition did not occur. For normal operation, CEN must be sampled low at rising edge of clock. Individual Byte I LOW Synchronous byte write enables. Each 9-bit byte has its own active low byte write enable. On load write BW1-BW4 Write Enables cycles (When R/W and ADV/LD are sampled low) the appropriate byte write signal (BW1-BW4) must be valid. The byte write signal must also be valid on each cycle of a burst write. Byte Write signals are ignored when R/W is sampled high. The appropriate byte(s) of data are written into the device one cycle later. BW1-BW4 can all be tied low if always doing write to the entire 36-bit word. Chip Enables I LOW Synchronous active low chip enable. CE1 and CE2 are used with CE2 to enable the IDT71V3557/59. (CE1 or CE1, CE2 CE2 sampled high or CE2 sampled low) and ADV/LD low at the rising edge of clock, initiates a deselect TM cycle. The ZBT has a one cycle deselect, i.e., the data bus will tri-state one clock cycle after deselect is initiated. CE2 Chip Enable I HIGH Synchronous active high chip enable. CE2 is used with CE1 and CE2 to enable the chip. CE2 has inverted polarity but otherwise identical to CE1 and CE2. CLK Clock I N/A This is the clock input to the IDT71V3557/59. Except for OE, all timing references for the device are made with respect to the rising edge of CLK. I/O0-I/O31 Data Input/Output I/O N/A Data input/output (I/O) pins. The data input path is registered, triggered by the rising edge of CLK. The data I/OP1-I/OP4 output path is flow-through (no output register). Linear Burst Order I LOW Burst order selection input. When LBO is high the Interleaved burst sequence is selected. When LBO is low LBO the Linear burst sequence is selected. LBO is a static input, and it must not change during device operation.. Output Enable I LOW Asynchronous output enable. OE must be low to read data from the 71V3557/59. When OE is HIGH the I/O OE pins are in a high-impedance state. OE does not need to be actively controlled for read and write cycles. In normal operation, OE can be tied low. TMS Test Mode Select I N/A Gives input command for TAP controller. Sampled on rising edge of TDK. This pin has an internal pullup. Serial input of registers placed between TDI and TDO. Sampled on rising edge of TCK. This pin has an TDI Test Data Input I N/A internal pullup. Clock input of TAP controller. Each TAP event is clocked. Test inputs are captured on rising edge of TCK, TCK Test Clock I N/A while test outputs are driven from the falling edge of TCK. This pin has an internal pullup. Serial output of registers placed between TDI and TDO. This output is active depending on the state of the TDO Test Data Output O N/A TAP controller. Optional Asynchronous JTAG reset. Can be used to reset the TAP controller, but not required. JTAG reset JTAG Reset ILOW occurs automatically at power up and also resets using TMS and TCK per IEEE 1149.1. If not used TRST can TRST (Optional) be left floating. This pin has an internal pullup. Synchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down the IDT71V3557/3559 to ZZ Sleep Mode I HIGH its lowest power consumption level. Data retention is guaranteed in Sleep Mode. This pin has an internal pulldown. VDD Power Supply N/A N/A 3.3V core power supply. VDDQ Power Supply N/A N/A 3.3V I/O Supply. VSS Ground N/A N/A Ground. 5282 tbl 02 NOTE: 1. All synchronous inputs must meet specified setup and hold times with respect to CLK. 6.422