Clk 71V3556S 128K x 36, 256K x 18 71V3558S 3.3V Synchronous ZBT SRAMs 71V3556SA 3.3V I/O, Burst Counter 71V3558SA Pipelined Outputs Features 4-word burst capability (interleaved or linear) 128K x 36, 256K x 18 memory configurations Individual byte write (BW1 - BW4) control (May tie active) Supports high performance system speed - 166 MHz (x36) Three chip enables for simple depth expansion (3.5 ns Clock-to-Data Access) TM 3.3V power supply (5%), 3.3V I/O Supply (VDDQ) ZBT Feature - No dead cycles between write and read Optional- Boundary Scan JTAG Interface (IEEE 1149.1 cycles compliant) Internally synchronized output buffer enable eliminates the Packaged in a JEDEC standard 100-pin plastic thin quad need to control OE flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch Positive clock-edge triggered address, data, and control ball grid array (fBGA) signal registers for fully pipelined applications Industrial temperature range (40C to +85C) is available Positive clock-edge triggered address, data, and control for selected speeds signal registers for fully pipelined applications Green parts available, see ordering information Single R/W (READ/WRITE) control pin Functional Block Diagram 128Kx36 BIT LBO MEMORY ARRAY Address A 0:16 DQ Address CE1, CE2, CE2 R/W DQ Control CEN ADV/LD DI DO BW/x DQ Control Logic Clk Mux Sel D Output Register Clock Q Gate OE 5281 drw 01a , TMS Data I/O 0:31 , JTAG I/O P 1:4 TDI TDO (SA Version) TCK TRST (optional) ZBT and Zero Bus Turnaround are trademarks of Renesas and the architecture is supported by Micron Technology and Motorola Inc. 1 Aug.06.21 Input RegisterClk 71V3556, 71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges Description The IDT71V3556/58 are 3.3V high-speed 4,718,592-bit (4.5 Mega- asserted when ADV/LD is low, no new memory operation can be bit) synchronous SRAMS. They are designed to eliminate dead bus initiated. However, any pending data transfers (reads or writes) will be cycles when turning the bus around between reads and writes, or completed. The data bus will tri-state two cycles after chip is deselected TM writes and reads. Thus, they have been given the name ZBT , or or a write is initiated. Zero Bus Turnaround. The IDT71V3556/58 has an on-chip burst counter. In the burst Address and control signals are applied to the SRAM during one mode, the IDT71V3556/58 can provide four cycles of data for a single clock cycle, and two cycles later the associated data cycle occurs, be address presented to the SRAM. The order of the burst sequence is it read or write. defined by the LBO input pin. The LBO pin selects between linear and The IDT71V3556/58 contain data I/O, address and control signal interleaved burst sequence. The ADV/LD signal is used to load a new registers. Output enable is the only asynchronous signal and can be external address (ADV/LD = LOW) or increment the internal burst used to disable the outputs at any given time. counter (ADV/LD = HIGH). A Clock Enable (CEN) pin allows operation of the IDT71V3556/58 The IDT71V3556/58 SRAMs utilize a high-performance CMOS to be suspended as long as necessary. All synchronous inputs are process and are packaged in a JEDEC standard 14mm x 20mm 100-pin ignored when (CEN) is high and the internal device registers will hold thin plastic quad flatpack (TQFP) as well as a 119 ball grid array (BGA) their previous values. and a 165 fine pitch ball grid array (fBGA). There are three chip enable pins (CE1, CE2, CE2) that allow the user to deselect the device when desired. If any one of these three are not Functional Block Diagram 256x18 BIT LBO MEMORY ARRAY Address A 0:17 DQ Address CE1, CE2, CE2 R/W DQ Control CEN ADV/LD DI DO BWx DQ Control Logic Clk Mux Sel D Output Register Clock Q Gate OE 5281 drw 01b , TMS Data I/O 0:15 , JTAG TDI TDO I/O P 1:2 (SA Version) TCK TRST (optional) 6.422 Aug.06.21 Input Register