GS881E18/32/36C(T/D)-xxx 250 MHz150 MHz 512K x 18, 256K x 32, 256K x 36 100-Pin TQFP & 165-bump BGA 2.5 V or 3.3 V V DD Commercial Temp 9Mb Sync Burst SRAMs 2.5 V or 3.3 V I/O Linear Burst Order (LBO) input. The Burst function need not Features be used. New addresses can be loaded on every cycle with no FT pin for user-configurable flow through or pipeline degradation of chip performance. operation Dual Cycle Deselect (DCD) operation Flow Through/Pipeline Reads IEEE 1149.1 JTAG-compatible Boundary Scan The function of the Data Output register can be controlled by 2.5 V or 3.3 V +10%/10% core power supply the user via the FT mode pin (Pin 14). Holding the FT mode 2.5 V or 3.3 V I/O supply881E18C pin low places the RAM in Flow Through mode, causing LBO pin for Linear or Interleaved Burst mode output data to bypass the Data Output Register. Holding FT Internal input resistors on mode pins allow floating mode pins high places the RAM in Pipeline mode, activating the rising- Default to Interleaved Pipeline mode edge-triggered Data Output Register. Byte Write (BW) and/or Global Write (GW) operation DCD Pipelined Reads Internal self-timed write cycle The GS881E18C(T/D)/GS881E32C(T/D)/GS881E36C(T/D) Automatic power-down for portable applications is a DCD (Dual Cycle Deselect) pipelined synchronous JEDEC-standard 100-lead TQFP and 165-bump BGA SRAM. SCD (Single Cycle Deselect) versions are also packages available. DCD SRAMs pipeline disable commands to the RoHS-compliant 100-lead TQFP and 165-bump BGA same degree as read commands. DCD RAMs hold the deselect packages available command for one full cycle and then begin turning off their outputs just after the second rising edge of clock. Functional Description36C Byte Write and Global Write Applications Byte write operation is performed by using Byte Write enable The GS881E18C(T/D)/GS881E32C(T/D)/GS881E36C(T/D) (BW) input combined with one or more individual byte write is a 9,437,184-bit high performance synchronous SRAM with signals (Bx). In addition, Global Write (GW) is available for a 2-bit burst address counter. Although of a type originally writing all bytes at one time, regardless of the Byte Write developed for Level 2 Cache applications supporting high control inputs. performance CPUs, the device now finds application in Sleep Mode synchronous SRAM applications, ranging from DSP main Low power (Sleep mode) is attained through the assertion store to networking chip set support. (High) of the ZZ signal, or by stopping the clock (CK). Controls Memory data is retained during Sleep mode. Addresses, data I/Os, chip enable (E1), address burst control Core and Interface Voltages inputs (ADSP, ADSC, ADV) and write control inputs (Bx, The GS881E18C(T/D)/GS881E32C(T/D)/GS881E36C(T/D) BW, GW) are synchronous and are controlled by a positive- operates on a 2.5 V or 3.3 V power supply. All input are 3.3 V edge-triggered clock input (CK). Output enable (G) and power and 2.5 V compatible. Separate output power (V ) pins are down control (ZZ) are asynchronous inputs. Burst cycles can DDQ used to decouple output noise from the internal circuits and are be initiated with either ADSP or ADSC inputs. In Burst mode, 3.3 V and 2.5 V compatible. subsequent burst addresses are generated internally and are controlled by ADV. The burst address counter may be configured to count in either linear or interleave order with the Parameter Synopsis -333 -300 -250 -200 -150 Unit t 2.5 2.5 2.5 3.0 3.8 ns KQ 3.0 3.3 4.0 5.0 6.7 ns Pipeline tCycle 3-1-1-1 Curr (x18) 240 225 195 170 140 mA Curr (x32/x36) 280 260 225 195 160 mA t 4.5 5.0 5.5 6.5 7.5 ns KQ 4.5 5.0 5.5 6.5 7.5 ns Flow Through tCycle 2-1-1-1 Curr (x18) 180 165 160 140 128 mA Curr (x32/x36) 205 190 180 160 145 mA Rev: 1.04 7/2012 1/37 2011, GSI Technology Specifications cited are subject to change without notice. For latest documentation see GS881E18/32/36C(T/D)-xxx GS881E18C 100-Pin TQFP Pinout (Package T) 10099 989796959493929190898887868584838281 A NC 1 80 NC NC 2 79 NC NC 3 78 V V DDQ 4 77 DDQ V V 5 76 SS SS NC NC 6 75 DQPA 7 NC 74 DQA DQB 8 73 DQA DQB 9 72 512K x 18 V V 10 71 SS SS V V 11 Top View 70 DDQ DDQ DQA DQB 12 69 DQA 13 DQB 68 V 14 FT 67 SS NC VDD 15 66 VDD NC 16 65 ZZ V 17 64 SS DQA DQB 18 63 DQA 19 62 DQB V V 20 61 DDQ DDQ V V 21 60 SS SS DQA 22 DQB 59 23 DQA DQB 58 NC DQPB 24 57 NC 25 56 NC V 26 55 V SS SS V 27 54 V DDQ DDQ NC 28 53 NC 29 52 NC NC 30 NC NC 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Note: Pins marked with NC can be tied to either V or V . These pins can also be left floating. DD SS Rev: 1.04 7/2012 2/37 2011, GSI Technology Specifications cited are subject to change without notice. For latest documentation see