128K x 36, 256K x 18 71V3576S 3.3V Synchronous SRAMs 71V3578S 3.3V I/O, Pipelined Outputs Burst Counter, Single Cycle Deselect Features 3.3V core power supply 128K x 36, 256K x 18 memory configurations Power down controlled by ZZ input Supports high system speed: 3.3V I/O Commercial and Industrial: Packaged in a JEDEC Standard 100-pin plastic thin quad 150MHz 3.8ns clock access time flatpack (TQFP) 133MHz 4.2ns clock access time Industrial temperature range (40C to +85C) is available LBO input selects interleaved or linear burst mode for selected speeds Self-timed write cycle with global write control (GW), byte write Green parts available, see ordering information enable (BWE), and byte writes (BWx) Functional Block Diagram LBO ADV INTERNAL Burst ADDRESS CEN Sequence 128K x 36/ CLK 2 Burst 17/18 Binary 256K x 18- Logic Counter ADSC A0* BIT Q0 CLR MEMORY A1* Q1 ADSP ARRAY 2 CLK EN A0,A1 A2A17 A0 - A16/17 ADDRESS 36/18 REGISTER 36/18 17/18 GW BWE Byte 1 Write Register Byte 1 Write Driver BW1 9 Byte 2 Write Register Byte 2 Write Driver BW2 9 Byte 3 Write Register Byte 3 Write Driver BW3 9 Byte 4 Byte 4 Write Register Write Driver BW4 9 OUTPUT REGISTER Q D CS0 Enable DATA CS1 Register INPUT REGISTER CLK EN ZZ Powerdown DQ Enable Delay Register OE OUTPUT BUFFER OE 36/18 I/O0 I/O31 I/OP1 I/OP4 5279 drw 01 1 May.01.2071V3576, 71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges Description The IDT71V3576/78 are high-speed SRAMs organized as access sequence. The first cycle of output data will be pipelined for one 128K x 36/256K x 18. The IDT71V3576/78 SRAMs contain write, data, cycle before it is available on the next rising clock edge. If burst mode address and control registers. Internal logic allows the SRAM to generate operation is selected (ADV=LOW), the subsequent three cycles of output a self-timed write based upon a decision which can be left until the end of data will be available to the user on the next three rising clock edges. The the write cycle. order of these three addresses are defined by the internal burst counter The burst mode feature offers the highest level of performance to the and the LBO input pin. system designer, as the IDT71V3576/78 can provide four cycles of data The IDT71V3576/78 SRAMs utilize a high-performance CMOS for a single address presented to the SRAM. An internal burst address process and are packaged in a JEDEC standard 14mm x 20mm 100-pin counter accepts the first cycle address from the processor, initiating the thin plastic quad flatpack (TQFP). Pin Description Summary A0-A17 Address Inputs Input Synchronous Chip Enable Input Synchronous CE CS0, CS1 Chip Selects Input Synchronous OE Output Enable Input Asynchronous Global Write Enable Input Synchronous GW BWE Byte Write Enable Input Synchronous (1) Individual Byte Write Selects Input Synchronous BW1, BW2, BW3, BW4 CLK Clock Input N/A ADV Burst Address Advance Input Synchronous Address Status (Cache Controller) Input Synchronous ADSC Address Status (Processor) Input Synchronous ADSP LBO Linear / Interleaved Burst Order Input DC ZZ Sleep Mode Input Asynchronous I/O0-I/O31, I/OP1-I/OP4 Data Input / Output I/O Synchronous VDD, VDDQ Core Power, I/O Power Supply N/A VSS Ground Supply N/A 5279 tbl 01 NOTE: 1. BW3 and BW4 are not applicable for the IDT71V3578. 6.422 May.01.20