71V3577S 128K X 36, 256K X 18 71V3579S 3.3V Synchronous SRAMs 3.3V I/O, Flow-Through Outputs Burst Counter, Single Cycle Deselect Features 128K x 36, 256K x 18 memory configurations Self-timed write cycle with global write control (GW), byte write Supports fast access times: enable (BWE), and byte writes (BWx) 3.3V core power supply Commercial: Power down controlled by ZZ input 6.5ns up to 133MHz clock frequency (TQFP package only) 3.3V I/O Commercial and Industrial: Packaged in a JEDEC Standard 100-pin plastic thin quad 7.5ns up to 117MHz clock frequency flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch ball 8.0ns up to 100MHz clock frequency grid array 8.5ns up to 87MHz clock frequency Industrial temperature range (40C to +85C) is available LBO input selects interleaved or linear burst mode for selected speeds Functional Block Diagram LBO ADV INTERNAL Burst ADDRESS CEN Sequence 128K x 36/ CLK 2 Burst 17/18 Binary 256K x 18- Logic Counter ADSC A0* BIT Q0 MEMORY CLR A1* ARRAY Q1 ADSP 2 CLK EN A0,A1 A2 - A17 ADDRESS A0 - A16/17 36/18 REGISTER 17/18 36/18 GW BWE Byte 1 Write Register Byte 1 Write Driver BW1 9 Byte 2 Write Register Byte 2 Write Driver BW2 9 Byte 3 Write Register Byte 3 Write Driver BW3 9 Byte 4 Byte 4 Write Register Write Driver BW4 9 CE Q D CS0 Enable DATA INPUT CS1 Register REGISTER CLK EN ZZ Powerdown OE OUTPUT BUFFER OE , 36/18 I/O0 - I/O31 I/OP1 - I/OP4 6450 drw 01 1 Apr.26.2171V3577S 79S, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges Description access sequence. The first cycle of output data will flow-through from the The IDT71V3577/79 are high-speed SRAMs organized as array after a clock-to-data access time delay from the rising clock edge of 128K x 36/256K x 18. The IDT71V3577/79 SRAMs contain write, data, the same cycle. If burst mode operation is selected (ADV=LOW), the address and control registers. There are no registers in the data output subsequent three cycles of output data will be available to the user on the path (flow-through architecture). Internal logic allows the SRAM to gen- next three rising clock edges. The order of these three addresses are erate a self-timed write based upon a decision which can be left until the defined by the internal burst counter and the LBO input pin. end of the write cycle. The IDT71V3577/79 SRAMs utilize a high-performance CMOS The burst mode feature offers the highest level of performance to the process and are packaged in a JEDEC standard 14mm x 20mm 100-pin system designer, as the IDT71V3577/79 can provide four cycles of data thin plastic quad flatpack (TQFP) as well as a 119 ball grid array (BGA) for a single address presented to the SRAM. An internal burst address and a 165 fine pitch ball grid array (fBGA). counter accepts the first cycle address from the processor, initiating the Pin Description Summary A0-A17 Address Inputs Input Synchronous CE Chip Enable Input Synchronous CS0, CS1 Chip Selects Input Synchronous OE Output Enable Input Asynchronous Global Write Enable Input Synchronous GW Byte Write Enable Input Synchronous BWE (1) Individual Byte Write Selects Input Synchronous 1, BW2, BW3, BW4 BW CLK Clock Input N/A ADV Burst Address Advance Input Synchronous ADSC Address Status (Cache Controller) Input Synchronous Address Status (Processor) Input Synchronous ADSP Linear / Interleaved Burst Order Input DC LBO ZZ Sleep Mode Input Asynchronous I/O0-I/O31, I/OP1-I/OP4 Data Input / Output I/O Synchronous VDD, VDDQ Core Power, I/O Power Supply N/A VSS Ground Supply N/A 6450tbl 01 NOTE: 1. BW3 and BW4 are not applicable for the IDT71V3579. 6.42 2 Apr.26.21