GS8342S08/09/18/36BD-400/350/333/300/250 TM 400 MHz250 MHz 165-Bump BGA 36Mb SigmaSIO DDR-II 1.8 V V Commercial Temp DD Burst of 2 SRAM Industrial Temp 1.8 V and 1.5 V I/O Features Clocking and Addressing Schemes Simultaneous Read and Write SigmaSIO Interface A Burst of 2SigmaSIO DDR-II SRAM is a synchronous JEDEC-standard pinout and package device. It employs dual input register clock inputs, K and K. Dual Double Data Rate interface The device also allows the user to manipulate the output Byte Write controls sampled at data-in time register clock input quasi independently with dual output DLL circuitry for wide output data valid window and future register clock inputs, C and C. If the C clocks are tied high, the frequency scaling K clocks are routed internally to fire the output registers Burst of 2 Read and Write instead. Each Burst of 2SigmaSIO DDR-II SRAM also 1.8 V +100/100 mV core power supply supplies Echo Clock outputs, CQ and CQ, which are 1.5 V or 1.8 V HSTL Interface synchronized with read data output. When used in a source Pipelined read operation synchronous clocking scheme, the Echo Clock outputs can be Fully coherent read and write pipelines used to fire input registers at the datas destination. ZQ mode pin for programmable output drive strength IEEE 1149.1 JTAG-compliant Boundary Scan Each internal read and write operation in a SigmaSIO DDR-II 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package B2 RAM is two times wider than the device I/O bus. An input RoHS-compliant 165-bump BGA package available data bus de-multiplexer is used to accumulate incoming data before it is simultaneously written to the memory array. An output data multiplexer is used to capture the data produced SigmaSIO Family Overview from a single memory array read and then route it to the GS8342S08/09/18/36BD are built in compliance with the appropriate output drivers as needed. Therefore, the address SigmaSIO DDR-II SRAM pinout standard for Separate I/O field of a SigmaSIO DDR-II B2 is always one address pin less synchronous SRAMs. They are 37,748,736-bit (36Mb) than the advertised index depth (e.g., the 4M x 8 has an 2M SRAMs. These are the first in a family of wide, very low addressable index). voltage HSTL I/O SRAMs designed to operate at the speeds needed to implement economical high performance networking systems. Parameter Synopsis -400 -350 -333 -300 -250 tKHKH 2.5 ns 2.86 ns 3.0 ns 3.3 ns 4.0 ns tKHQV 0.45 ns 0.45 ns 0.45 ns 0.45 ns 0.45 ns Rev: 1.02b 8/2017 1/35 2011, GSI Technology Specifications cited are subject to change without notice. For latest documentation see GS8342S08/09/18/36BD-400/350/333/300/250 4M x 8 SigmaQuad SRAMTop View 1 2 3 4 5 6 7 8 9 10 11 NC/SA NC/SA A CQ SA R/W NW1 K LD SA SA CQ (72Mb) (144Mb) NC/SA B NC NC NC SA K NW0 SA NC NC Q3 (288Mb) C NC NC NC V SA SA SA V NC NC D3 SS SS D NC D4 NC V V V V V NC NC NC SS SS SS SS SS E NC NC Q4 V V V V V NC D2 Q2 DDQ SS SS SS DDQ F NC NC NC V V V V V NC NC NC DDQ DD SS DD DDQ G NC D5 Q5 V V V V V NC NC NC DDQ DD SS DD DDQ H D V V V V V V V V V ZQ OFF REF DDQ DDQ DD SS DD DDQ DDQ REF J NC NC NC V V V V V NC Q1 D1 DDQ DD SS DD DDQ K NC NC NC V V V V V NC NC NC DDQ DD SS DD DDQ L NC Q6 D6 V V V V V NC NC Q0 DDQ SS SS SS DDQ M NC NC NC V V V V V NC NC D0 SS SS SS SS SS N NC D7 NC V SA SA SA V NC NC NC SS SS P NC NC Q7 SA SA C SA SA NC NC NC R TDO TCK SA SA SA C SA SA SA TMS TDI 11 x 15 Bump BGA13 x 15 mm Body1 mm Bump Pitch Notes: 1. NW0 controls writes to D0:D3. NW1 controls writes to D4:D7. 2. A2, A7, and B5 are the expansion addresses. Rev: 1.02b 8/2017 2/35 2011, GSI Technology Specifications cited are subject to change without notice. For latest documentation see