HIGH-SPEED 128K x 8 IDT709099L
SYNCHRONOUS PIPELINED
DUAL-PORT STATIC RAM
Features
True Dual-Ported memory cells which allow simultaneous additional logic
access of the same memory location Full synchronous operation on both ports
High-speed clock to data access 4ns setup to clock and 0ns hold on all control, data, and
Commercial: 7.5/9/12ns (max.) address inputs
Industrial: 9ns (max.) Data input, address, and control registers
Low-power operation Fast 7.5ns clock to data out in the Pipelined output mode
IDT709099L Self-timed write allows fast cycle time
Active: 1.2W (typ.) 12ns cycle time, 83MHz operation in Pipelined output mode
Standby: 2.5mW (typ.) TTL- compatible, single 5V (10%) power supply
Flow-Through or Pipelined output mode on either Port via Industrial temperature range (40C to +85C) is
the FT/PIPE pins available for selected speeds
Counter enable and reset features Available in a 100-pin Thin Quad Flatpack (TQFP) package
Dual chip enables allow for depth expansion without
Functional Block Diagram
R/WL R/WR
OEL OER
CE0L
CE0R
1
1
CE1L
CE1R
0
0
0/1
0/1
1
1 0 0
0/1 0/1
FT/PIPEL FT/PIPER
I/O0L-I/O7L
I/O0R - I/O7R
I/O I/O
Control Control
A16L A16R
Counter/
Counter/
MEMORY A0R
A0L Address
Address
ARRAY CLKR
CLKL Reg.
Reg.
ADSR
ADSL
CNTENR
CNTENL
CNTRSTR
CNTRSTL
4846 drw 01
JANUARY 2009
1
DSC-4846/6
2009 Integrated Device Technology, Inc.IDT709099L
High-Speed 128K x 8 Synchronous Pipelined Dual-Port Static RAM Industrial and Commercial Temperature Ranges
Description
The IDT709099 is a high-speed 128K x 8 bit synchronous Dual- With an input data register, the IDT709099 has been optimized for
applications having unidirectional or bidirectional data flow in bursts.
Port RAM. The memory array utilizes Dual-Port memory cells to allow
An automatic power down feature, controlled by CE0 and CE1, permits
simultaneous access of any address from both ports. Registers on
control, data, and address inputs provide minimal setup and hold the on-chip circuitry of each port to enter a very low standby power
times. The timing latitude provided by this approach allows systems mode. Fabricated using IDTs CMOS high-performance technology,
these devices typically operate on only 1.2W of power.
to be designed with very short cycle times.
(1,2,3)
Pin Configurations
Index
11/09/01
1009998 97 9695 94 93 92 9190 89 88 8786 8584 8382 81 8079 7877 76
1 NC
NC
75
2
NC 74 NC
3 73 A7R
A7L
4 72 A8R
A8L
5 71 A9R
A9L
6 70 A10R
A10L
7 69 A11R
A11L
8 68 A12R
A12L
67
9 A13R
A13L
10 66 A14R
A14L
IDT709099PF
65
11 A15R
A15L (4)
PN100-1
12 64 A16R
A16L
63
VCC 13 100-PIN TQFP GND
(5)
14 TOP VIEW 62 NC
NC
61 NC
NC 15
60
16 NC
NC
59
NC 17 NC
58
18 CE0R
CE0L
57
19 CE1R
CE1L
.
56
20 CNTRSTR
CNTRSTL
55
21 R/WR
R/WL
54
OEL 22 OER
53
FT/PIPER
FT/PIPEL 23
52
NC 24 GND
51
25 NC
NC
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
4846 drw 02
NOTES:
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground.
3. Package body is approximately 14mm x 14mm x 1.4mm
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
6.422
GND NC
NC NC
L
I/O7L A6
A5L
I/O6L
A4L
I/O5L
A3L
I/O4L
I/O3L A2L
A1L
I/O2L
GND A0L
CNTENL
I/O1L
I/O0L CLKL
ADSL
VCC
GND
GND
I/O0R ADSR
R
I/O1R CLK
I/O2R CNTENR
0R
A
VCC
A1R
I/O3R
A2R
I/O4R
A3R
I/O5R
A4R
I/O6R
A5R
I/O7R
NC A6R
NC NC
NC
NC