HIGH SPEED IDT7130SA/LA 1K X 8 DUAL-PORT IDT7140SA/LA STATIC SRAM Features On-chip port arbitration logic (IDT7130 Only) High-speed access BUSY output flag on IDT7130 BUSY input on IDT7140 Commercial: 20/25/35/55/100ns (max.) INT flag for port-to-port communication Industrial: 25/55/100ns (max.) Fully asynchronous operation from either port Military: 25/35/55/100ns (max.) Battery backup operation2V data retention (LA only) Low-power operation TTL-compatible, single 5V 10% power supply IDT7130/IDT7140SA Military product compliant to MIL-PRF-38535 QML Active: 550mW (typ.) Industrial temperature range (40C to +85C) is available Standby: 5mW (typ.) for selected speeds IDT7130/IDT7140LA Available in 48-pin DIP, LCC and Ceramic Flatpack, 52-pin Active: 550mW (typ.) PLCC, and 64-pin STQFP and TQFP Standby: 1mW (typ.) MASTER IDT7130 easily expands data bus width to 16-or- Green parts available, see ordering information more-bits using SLAVE IDT7140 Functional Block Diagram OER OEL CEL CER R/WL R/WR , I/O0L- I/O7L I/O0R-I/O7R I/O I/O Control Control (1,2) (1,2) BUSYL BUSYR A9L A9R Address MEMORY Address Decoder ARRAY Decoder A0R A0L 10 10 ARBITRATION and CEL CER INTERRUPT OEL OER LOGIC R/WR R/WL (2) (2) INTR INTL 2689 drw 01 NOTES: 1. IDT7130 (MASTER): BUSY is open drain output and requires pullup resistor. IDT7140 (SLAVE): BUSY is input. 2. Open drain output: requires pullup resistor. MAY 2016 1 2016 Integrated Device Technology, Inc. DSC-2689/16 IDT7130SA/LA and IDT7140SA/LA High-Speed 1K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges Description The IDT7130/IDT7140 are high-speed 1K x 8 Dual-Port Static of each port to enter a very low standby power mode. RAMs. The IDT7130 is designed to be used as a stand-alone 8-bit Fabricated using CMOS high-performance technology, these de- Dual-Port RAM or as aMASTE Dual-Port RAM together with the vices typically operate on only 550mW of power. Low-power (LA) IDT7140SLAV Dual-Port in 16-bit-or-more word width systems. versions offer battery backup data retention capability, with each Dual- Using the IDT MASTER/SLAVE Dual-Port RAM approach in 16-or- Port typically consuming 200W from a 2V battery. more-bit memory system applications results in full-speed, error- The IDT7130/IDT7140 devices are packaged in 48-pin sidebraze free operation without the need for additional discrete logic. or plastic DIPs, LCCs, flatpacks, 52-pin PLCC, and 64-pin TQFP Both devices provide two independent ports with separate con- and STQFP. Military grade products are manufactured in compli- trol, address, and I/O pins that permit independent asynchronous ance with the latest revision of MIL-PRF-38535 QML, making it access for reads or writes to any location in memory. An automatic ideally suited to military temperature applications demanding the power down feature, controlled by CE, permits the on chip circuitry highest level of performance and reliability. (1,2,3) Pin Configurations 42 41 40 39 38 37 36 35 34 33 32 31 OER I/O5R 43 30 INTR I/O4R 44 29 BUSYR I/O3R 45 28 R/WR 46 27 I/O2R CER I/O1R 47 26 VCC 25 48 7130/40 I/O0R (4) F48 CEL GND 1 24 R/WL 2 23 I/O7L I/O6L BUSYL 3 22 INTL I/O5L 4 21 OEL 20 I/O4L 5 I/O3L A0L 6 19 7 8 9 10 11 12 13 14 15 16 17 18 2689 drw 03F INDEX 18 17 16 15 14 13 12 11 10 9 8 7 19 6 A0L I/O3L 20 I/O4L 5 OEL 21 4 I/O5L INTL 22 3 BUSYL I/O6L I/O7L 23 2 R/WL 24 1 GND CEL 7130/40 (4) L48 48 I/O0R 25 VCC 26 47 I/O1R CER 46 I/O2R 27 R/WR I/O3R 28 45 BUSYR 44 29 INTR I/O4R I/O5R 30 43 OER NOTES: 31 32 33 34 35 36 37 38 39 40 41 42 1. All VCC pins must be connected to power supply. 2. All GND pins must be connected to ground supply. 3. L48 package body is approximately .57 in x .57 in x .68 in. 2689 drw 03L F48 package body is approximately .75 in x .75 in x .11 in. 4. This package code is used to reference the package diagram. 2 A1L A0R A2L A1R A2R A3L A3R A4L A5L A4R A6L A5R A7L A6R A7R A8L A9L A8R A9R I/O0L I/O1L I/O7R I/O2L I/O6R I/O6R I/O2L I/O7R I/O1L A9R I/O0L A8R A9L A7R A8L A6R A7L A6L A5R A4R A5L A4L A3R A2R A3L A1R A2L A0R A1L