HIGH-SPEED 7134SA/LA 4K x 8 DUAL-PORT STATIC SRAM Features Fully asynchronous operation from either port High-speed access Commercial: 20/55ns (max.) Battery backup operation2V data retention (LA only) Industrial: 25ns (max.) TTL-compatible single 5V (10%) power supply Available in 48-pin DIP, LCC, Flatpack and 52-pin PLCC Military: 35/45/55/70ns (max.) Military product compliant to MIL-PRF-38535 QML Low-power operation IDT7134SA Industrial temperature range (40C to +85C) is available for Active: 700mW (typ.) selected speeds Green parts available, see ordering information Standby: 5mW (typ.) IDT7134LA Active: 700mW (typ.) Standby: 1mW (typ.) Functional Block Diagram R/WL R/WR CER CEL OEL OER I/O I/O I/O0L- I/O7L I/O0R-I/O7R CONTROL CONTROL ADDRESS ADDRESS MEMORY A0L-A11L A0R-A11R DECODER DECODER ARRAY 2720 drw 01 1 May.10. 217134SA/LA High-Speed 4K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges Description The IDT7134 is a high-speed 4K x 8 Dual-Port Static RAM controlled by CE, permits the on-chip circuitry of each port to enter a very designed to be used in systems where on-chip hardware port arbitration low standby power mode. is not needed. This part lends itself to those systems which cannot Fabricated using CMOS high-performance technology, these Dual- tolerate wait states or are designed to be able to externally arbitrate or Ports typically operate on only 700mW of power. Low-power (LA) withstand contention when both sides simultaneously access the versions offer battery backup data retention capability, with each port same Dual-Port RAM location. typically consuming 200W from a 2V battery. The IDT7134 provides two independent ports with separate control, The IDT7134 is packaged in either a sidebraze or plastic 48-pin DIP, address, and I/O pins that permit independent, asynchronous access 48-pin LCC, 52-pin PLCC and 48-pin Flatpack. Military grade product is for reads or writes to any location in memory. It is the users responsibility manufactured in compliance with MIL-PRF-38535 QML, making it ideally to ensure data integrity when simultaneously accessing the same suited to military temperature applications demanding the highest level of memory location from both ports. An automatic power down feature, performance and reliability. (1,2,3) Pin Configurations CEL CC 1 48 V CER R/WL 2 47 3 46 R/WR A11L A10L 4 45 A11R OEL 5 44 A10R 7134 A0L 6 43 OER A1L 7 42 A0R (4) PDG48 A2L 8 41 A1R or A3L 9 (4) 40 A2R SB48 A4L 10 39 A3R A5L 11 38 A4R A6L 12 37 A5R 48-Pin DIP A7L 13 36 A6R (5) Top View A8L 14 35 A7R A9L 15 34 A8R I/O 0L 16 33 A9R 20 19 18 17 16 15 14 13 12 11 10 9 8 1L I/O4L I/O 17 32 I/O7R 21 7 A0L I/O 2L 18 31 I/O6R I/O5L 22 6 OEL I/O 3L 19 30 I/O5R 5 I/O6L 23 A10L I/O 4L 20 29 I/O4R I/O 5L 21 28 I/O3R 4 I/O7L 24 A11L 6L I/O 22 27 I/O2R 3 25 N/C N/C 7L I/O 23 26 I/O1R 7134 GND 24 25 I/O0R GND 26 2 R/WL (4) PLG52 , 1 I/O0R 27 CEL 2720 drw 02a 52-Pin PLCC I/O1R VCC 28 52 Top View I/O2R 29 51 CER I/O3R 30 R/WR 50 I/O4R 31 49 N/C I/O5R 32 A11R 48 I/O6R 33 47 A10R 34 35 36 37 38 39 40 41 42 43 44 45 46 2720 drw 03 NOTES: 1. All VCC pins must be connected to the power supply. 2. All GND pins must be connected to the ground supply. 3. PDG48 package body is approximately .55 in x 2.43 in x .18 in. SB48 package body is approximately .62 in x 2.43 in x .15 in. PLG52 package body is approximately .75 in x .75 in x .17 in. 4. This package code is used to reference the package diagram. 5. This text does not indicate orientation of actual part-marking. 2 May.10. 21 I/O7R I/O3L N/C I/O2L A9R I/O1L A8R I/O0L A7R A9L A6R A8L A5R A7L A4R A6L A3R A5L A2R A4L A1R A3L A0R A2L OER A1L