512K x 36, 1M x 18
IDT71T75602
2.5V Synchronous ZBT SRAMs
IDT71T75802
2.5V I/O, Burst Counter
Pipelined Outputs
Features Description
The IDT71T75602/802 are 2.5V high-speed 18,874,368-bit
512K x 36, 1M x 18 memory configurations
(18 Megabit) synchronous SRAMs. They are designed to eliminate dead
Supports high performance system speed - 200 MHz
bus cycles when turning the bus around between reads and writes, or
(3.2 ns Clock-to-Data Access)
TM
TM
writes and reads. Thus, they have been given the name ZBT , or Zero
ZBT Feature - No dead cycles between write and read
Bus Turnaround.
cycles
Address and control signals are applied to the SRAM during one
Internally synchronized output buffer enable eliminates the
clock cycle, and two cycles later the associated data cycle occurs, be it
need to control OE
read or write.
Single R/W (READ/WRITE) control pin
The IDT71T75602/802 contain data I/O, address and control signal
Positive clock-edge triggered address, data, and control
registers. Output enable is the only asynchronous signal and can be used
signal registers for fully pipelined applications
to disable the outputs at any given time.
4-word burst capability (interleaved or linear)
A Clock Enable CEN pin allows operation of the IDT71T75602/802
Individual byte write (BW1 - BW4) control (May tie active)
to be suspended as long as necessary. All synchronous inputs are ignored
Three chip enables for simple depth expansion
when (CEN) is high and the internal device registers will hold their previous
2.5V power supply (5%)
values.
2.5V I/O Supply (VDDQ)
There are three chip enable pins (CE1, CE2, CE2) that allow the
Power down controlled by ZZ input
user to deselect the device when desired. If any one of these three is not
Boundary Scan JTAG Interface (IEEE 1149.1 Compliant)
asserted when ADV/LD is low, no new memory operation can be initiated.
Packaged in a JEDEC standard 100-pin plastic thin quad
However, any pending data transfers (reads or writes) will be completed.
flatpack (TQFP), 119 ball grid array (BGA)
Pin Description Summary
A0-A19 Address Inputs Input Synchronous
Chip Enables Input Synchronous
CE1, CE2, CE2
OE Output Enable Input Asynchronous
R/W Read/Write Signal Input Synchronous
Clock Enable Input Synchronous
CEN
Individual Byte Write Selects Input Synchronous
BW1, BW2, BW3, BW4
CLK Clock Input N/A
ADV/LD Advance burst address / Load new address Input Synchronous
Linear / Interleaved Burst Order Input Static
LBO
TMS Test Mode Select Input N/A
TDI Test Data Input Input N/A
TCK Test Clock Input N/A
TDO Test Data Input Output N/A
TRST JTAG Reset (Optional) Input Asynchronous
ZZ Sleep Mode Input Synchronous
I/O0-I/O31, I/OP1-I/OP4 Data Input / Output I/O Synchronous
VDD, VDDQ Core Power, I/O Power Supply Static
VSS Ground Supply Static
5313 tbl 01
APRIL 2012
1
2012 Integrated Device Technology, Inc. DSC-5313/10IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
Description (cont.)
used to load a new external address (ADV/LD = LOW) or increment
The data bus will tri-state two cycles after the chip is deselected or a write
the internal burst counter (ADV/LD = HIGH).
is initiated.
The IDT71T75602/802 SRAMs utilize a high-performance 2.5V
The IDT71T75602/802 have an on-chip burst counter. In the burst
CMOS process, and are packaged in a JEDEC Standard 14mm x 20mm
mode, the IDT71T75602/802 can provide four cycles of data for a
100pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array
single address presented to the SRAM. The order of the burst
(BGA).
sequence is defined by the LBO input pin. The LBO pin selects
between linear and interleaved burst sequence. The ADV/LD signal is
(1)
Pin Definitions
Symbol Pin Function I/O Active Description
A0-A19 Address Inputs I N/A Synchronous Address inputs. The address register is triggered by a combination of the rising edge of CLK,
ADV/LD low, CEN low, and true chip enables.
ADV/LD Advance / Load I N/A ADV/LD is a synchronous input that is used to load the internal registers with new address and control when it is
sampled low at the rising edge of clock with the chip selected. When ADV/LD is low with the chip deselected,
any burst in progress is terminated. When ADV/LD is sampled high then the internal burst counter is advanced
for any burst that was in progress. The external addresses are ignored when ADV/LD is sampled high.
R/W Read / Write I N/A R/W signal is a synchronous input that identifies whether the current load cycle initiated is a Read or Write access
to the memory array. The data bus activity for the current cycle takes place two clock cycles later.
CEN Clock Enable I LOW Synchronous Clock Enable Input. When CEN is sampled high, all other synchronous inputs, including clock are
ignored and outputs remain unchanged. The effect of CEN sampled high on the device outputs is as if the low
to high clock transition did not occur. For normal operation, CEN must be sampled low at rising edge of clock.
Individual Byte I LOW Synchronous byte write enables. Each 9-bit byte has its own active low byte write enable. On load write cycles
BW1-BW4
Write Enables (when R/W and ADV/LD are sampled low) the appropriate byte write signal (BW1-BW4) must be valid. The byte
write signal must also be valid on each cycle of a burst write. Byte Write signals are ignored when R/W is sampled
high. The appropriate byte(s) of data are written into the device two cycles later. BW1-BW4 can all be tied low if
always doing write to the entire 36-bit word.
Chip Enables I LOW Synchronous active low chip enable. CE1 and CE2 are used with CE2 to enable the IDT71T75602/802 (CE1 or CE2
CE1, CE2
sampled high or CE2 sampled low) and ADV/LD low at the rising edge of clock, initiates a deselect cycle. The
TM
ZBT has a two cycle deselect, i.e., the data bus will tri-state two clock cycles after deselect is initiated.
CE2 Chip Enable I HIGH Synchronous active high chip enable. CE2 is used with CE1 and CE2 to enable the chip. CE2 has inverted polarity
but otherwise identical to CE1 and CE2.
CLK Clock I N/A This is the clock input to the IDT71T75602/802. Except for OE, all timing references for the device are made with
respect to the rising edge of CLK.
I/O0-I/O31 Data Input/Output I/O N/A Synchronous data input/output (I/O) pins. Both the data input path and data output path are reg istered and triggered
I/OP1-I/OP4 by the rising edge of CLK.
Linear Burst Order I LOW Burst order selection input. When LBO is high the Interleaved burst sequence is selected. When LBO is low the
LBO
Linear burst sequence is selected. LBO is a static input and it must not change during device operation.
Output Enable I LOW Asynchronous output enable. OE must be low to read data from the 71T75602/802. When OE is high the I/O pins
OE
are in a high-impedance state.OE does not need to be actively controlled for read and write cycles. In normal
operation, OE can be tied low.
TMS Test Mode Select I N/A Gives input command for TAP controller. Sampled on rising edge of TDK. This pin has an internal pullup.
Serial input of registers placed between TDI and TDO. Sampled on rising edge of TCK. This pin has an internal
TDI Test Data Input I N/A
pullup.
Clock input of TAP controller. Each TAP event is clocked. Test inputs are captured on rising edge of TCK, while
TCK Test Clock I N/A
test outputs are driven from the falling edge of TCK. This pin has an internal pullup.
Serial output of registers placed between TDI and TDO. This output is active depending on the state of the TAP
TDO Test Data Output O N/A
controller.
Optional asynchronous JTAG reset. Can be used to reset the TAP controller, but not required. JTAG reset occurs
JTAG Reset
TRST ILOW automatically at power up and also resets using TMS and TCK per IEEE 1149.1. If not used TRST can be left
(Optional)
floating. This pin has an internal pullup. Only available in BGA package.
Synchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down the IDT71T75602/802 to its
ZZ Sleep Mode I HIGH
lowest power consumption level. Data retention is guaranteed in Sleep Mode. This pin has an internal pulldown.
VDD Power Supply N/A N/A 2.5V core power supply.
VDDQ Power Supply N/A N/A 2.5V I/O Supply.
VSS Ground N/A N/A Ground.
5313 tbl 02
NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
6.422