1M x 18 71T75902 2.5V Synchronous ZBT SRAM 2.5V I/O, Burst Counter Flow-Through Outputs Features Three chip enables for simple depth expansion 1M x 18 memory configuration 2.5V power supply (5%) Supports high performance system speed - 100 MHz 2.5V (5%) I/O Supply (VDDQ) (7.5 ns Clock-to-Data Access) Power down controlled by ZZ input TM ZBT Feature - No dead cycles between write and read cycles Boundary Scan JTAG Interface (IEEE 1149.1 Compliant) Internally synchronized output buffer enable eliminates the Packaged in a JEDEC standard 100-pin plastic thin quad need to control OE flatpack (TQFP), 119 ball grid array (BGA) Single R/W (READ/WRITE) control pin Industrial temperature range (40C to +85C) is available 4-word burst capability (Interleaved or linear) for selected speeds Individual byte write (BW1 - BW2 control (May tie active) Green parts available, see Ordering Information Functional Block Diagram 1M x 18 LBO 1M x 18 BIT MEMORY ARRAY Address A 0:19 D Q Address CE1, CE2, CE2 R/W D Q Control CEN ADV/LD DI DO BWx D Q Control Logic Clk Mux Sel Clock Gate OE TMS Data I/O 0:15 , I/O P 1:2 TDI 5319 drw 01a TDO JTAG TCK TRST (optional) 1 Apr.07.20 Input Register71T75902 1M x 18, 2.5V Synchronous ZBT SRAM with 2.5V I/O, Burst Counter and Flow-Through Outputs Commercial and Industrial Temperature Ranges Description There are three chip enable pins (CE1, CE2, CE2) that allow the user The IDT71T75902 is a 2.5V high-speed 18,874,368-bit (18 Megabit) to deselect the device when desired. If any one of these three is not synchronous SRAM organized as 1M x 18. It is designed to eliminate asserted when ADV/LD is low, no new memory operation can be initiated. dead bus cycles when turning the bus around between reads and writes, However, any pending data transfers (reads or writes) will be completed. TM or writes and reads. Thus it has been given the name ZBT , or Zero Bus The data bus will tri-state one cycle after the chip is deselected or a write Turnaround. is initiated. Address and control signals are applied to the SRAM during one The IDT71T75902 has an on-chip burst counter. In the burst mode, clock cycle, and on the next clock cycle the associated data cycle occurs, the IDT71T75902 can provide four cycles of data for a single address be it read or write. presented to the SRAM. The order of the burst sequence is defined by the LBO input pin. The LBO pin selects between linear and interleaved burst The IDT71T75902 contain address, data-in and control signal regis- sequence. The ADV/LD signal is used to load a new external address ters. The outputs are flow-through (no output data register). Output enable (ADV/LD = LOW) or increment the internal burst counter (ADV/LD = is the only asynchronous signal and can be used to disable the outputs HIGH). at any given time. The IDT71T75902 SRAM utilizes a high-performance CMOS pro- A Clock Enable (CEN) pin allows operation of the IDT71T75902 to be cess, and are packaged in a JEDEC Standard 14mm x 20mm 100-pin suspended as long as necessary. All synchronous inputs are plastic thin quad flatpack (TQFP) as well as a 119 ball grid array (BGA). ignored when CEN is high and the internal device registers will hold their previous values. Pin Description Summary A0-A19 Address Inputs Input Synchronous Chip Enables Input Synchronous CE1, CE2, CE2 Output Enable Input Asynchronous OE R/W Read/Write Signal Input Synchronous Clock Enable Input Synchronous CEN Individual Byte Write Selects Input Synchronous BW1, BW2 CLK Clock Input N/A ADV/LD Advance Burst Address/Load New Address Input Synchronous Linear/Interleaved Burst Order Input Static LBO TMS Test Mode Select Input N/A TDI Test Data Input Input N/A TCK Test Clock Input N/A TDO Test Data Output Output N/A JTAG Reset (Optional) Input Asynchronous TRST ZZ Sleep Mode Input Synchronous I/O0-I/O31, I/OP1-I/OP2 Data Input/Output I/O Synchronous VDD, VDDQ Core Power, I/O Power Supply Static VSS Ground Supply Static 5319 tbl 01a 6.42 2 Apr.07.20