Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as Cypress document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.comCY62148EV30 MoBL 4-Mbit (512K 8) Static RAM 4-Mbit (512K 8) Static RAM Features Functional Description Very high speed: 45 ns The CY62148EV30 is a high performance CMOS static RAM organized as 512K words by 8 bits. This device features Wide voltage range: 2.20 V to 3.60 V advanced circuit design to provide ultra low active current. This Temperature range: is ideal for providing More Battery Life (MoBL ) in portable Industrial: 40 C to +85 C applications such as cellular telephones. The device also has an Automotive-A: 40 C to +85 C automatic power down feature that significantly reduces power consumption. Placing the device into standby mode reduces Pin compatible with CY62148DV30 power consumption by more than 99 percent when deselected (CE HIGH). The eight input and output pins (I/O through I/O ) Ultra low standby power 0 7 are placed in a high impedance state when the device is Typical standby current: 2.5 A deselected (CE HIGH), the outputs are disabled (OE HIGH), or Maximum standby current: 7 A (Industrial) during a write operation (CE LOW and WE LOW). Ultra low active power To write to the device, take Chip Enable (CE) and Write Enable Typical active current: 3.5 mA at f = 1 MHz (WE) inputs LOW. Data on the eight I/O pins (I/O through I/O ) 0 7 is then written into the location specified on the address pins (A Easy memory expansion with CE and OE features 0 through A ). 18 Automatic power down when deselected To read from the device, take Chip Enable (CE) and Output Complementary metal oxide semiconductor (CMOS) for Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under optimum speed and power these conditions, the contents of the memory location specified by the address pins appear on the I/O pins. Available in Pb-free 36-ball very fine-pitch ball grid array For a complete list of related 1documentation, click here. (VFBGA), 32-pin thin small outline package (TSOP) II, and 1 32-pin small outline integrated circuit (SOIC) packages Logic Block Diagram I/O 0 A 0 INPUT BUFFER IO 0 A 1 I/O 1 A 2 IO 1 A 3 I/O 2 A 4 IO 2 A 5 I/O 3 A 6 512K x 8 IO 3 A 7 I/O 4 A 8 ARRAY IO 4 A 9 I/O 5 A 10 IO 5 A 11 I/O 6 A 12 IO 6 I/O 7 CE POWER IO 7 COLUMN DECODER WE DOWN OE Note 1. SOIC package is available only in 55 ns speed bin. Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-05576 Rev. *X Revised June 26, 2020 ROW DECODER A 13 A 14 A 15 A 16 A 17 A 18 SENSE AMPS