Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as Cypress document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.comCY62147G/CY621472G CY62147GE MoBL 4-Mbit (256K words 16-bit) Static RAM with Error-Correcting Code (ECC) 4-Mbit (256K words 16-bit) Static RAM with Error-Correcting Code (ECC) Data writes are performed by asserting the Write Enable (WE) Features input LOW, while providing the data on I/O through I/O and 0 15 High speed: 45 ns/55 ns address on A through A pins. The Byte High Enable (BHE) 0 17 and Byte Low Enable (BLE) inputs control write operations to the Ultra-low standby power upper and lower bytes of the specified memory location. BHE Typical standby current: 3.5 A controls I/O through I/O and BLE controls I/O through I/O . 8 15 0 7 Maximum standby current: 8.7 A Data reads are performed by asserting the Output Enable (OE) 1, 2 Embedded ECC for single-bit error correction input and providing the required address on the address lines. Wide voltage range: 1.65 V to 2.2 V, 2.2 V to 3.6 V, and 4.5 V Read data is accessible on the I/O lines (I/O through I/O ). 0 15 to 5.5 V Byte accesses can be performed by asserting the required byte enable signal (BHE or BLE) to read either the upper byte or the 1.0-V data retention lower byte of data from the specified address location. TTL-compatible inputs and outputs All I/Os (I/O through I/O ) are placed in a HI-Z state when the 0 15 Error indication (ERR) pin to indicate 1-bit error detection and device is deselected (CE HIGH for a single chip enable device correction and CE HIGH/CE LOW for a dual chip enable device), or 1 2 control signals are de-asserted (OE, BLE, BHE). Pb-free 48-ball VFBGA and 44-pin TSOP II packages The device also has a unique Byte Power down feature, where, Functional Description if both the Byte Enables (BHE and BLE) are disabled, the devices seamlessly switch to standby mode irrespective of the CY62147G and CY62147GE are high-performance CMOS state of the chip enables, thereby saving power. low-power (MoBL) SRAM devices with embedded ECC. Both devices are offered in single and dual chip enable options and in On the CY62147GE devices, the detection and correction of a multiple pin configurations. The CY62147GE device includes an single-bit error in the accessed location is indicated by the 1 ERR pin that signals an error-detection and correction event assertion of the ERR output (ERR = HIGH) . See the Truth during a read cycle. Table CY62147G/CY62147GE on page 16 for a complete description of read and write modes. Devices with a single chip enable input are accessed by asserting the chip enable (CE) input LOW. Dual chip enable The logic block diagrams are on page 2. devices are accessed by asserting both chip enable inputs CE 1 as low and CE as HIGH. 2 Product Portfolio Power Dissipation Features and Options Operating I , (mA) CC 3 Standby, I (A) SB2 Product Range V Range (V) Speed (ns) (see the Pin CC f = f max Configurations 4 4 Typ Max Typ Max section) CY62147G(E)18 Industrial 1.65 V2.2 V 55 15 20 3.5 10 Single or dual CY62147G(E)30 Chip Enables 2.2 V3.6 V 45 15 20 3.5 8.7 CY621472G30 Optional ERR CY62147G(E) 4.5 V5.5 V pin Notes 1. This device does not support automatic write-back on error detection. 2. SER FIT Rate <0.1 FIT/Mb. Refer AN88889 for details. 3. The ERR pin is available only for devices which have ERR option E in the ordering code. Refer Ordering Information on page 17. 4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = 1.8 V (for a V range of 1.65 V2.2 V), CC CC V =3V (for V range of 2.2 V3.6 V), and V = 5 V (for V range of 4.5 V5.5 V), T = 25 C. CC CC CC CC A Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-92847 Rev. *K Revised July 13, 2018