7052S/L HIGH-SPEED TM 2K x 8 FourPort STATIC RAM Features Battery backup operation2V data retention High-speed access TTL-compatible single 5V (10%) power supply Commercial: 20/25/35ns (max.) Available in 120 pin Thin Quad Flatpacks and 108 pin PGA Industrial: 25ns (max.) Military product compliant to MIL-PRF-38535 QML Military: 35ns (max.) Industrial temperature range (40C to +85C) is available Low-power operation for selected speeds IDT7052S Green parts available, see ordering information Active: 750mW (typ.) Standby: 7.5mW (typ.) IDT7052L Description Active: 750mW (typ.) The IDT7052 is a high-speed 2K x 8 FourPort Static RAM designed Standby: 1.5mW (typ.) to be used in systems where multiple access into a common RAM is True FourPort memory cells which allow simultaneous required. This FourPort Static RAM offers increased system performance access of the same memory locations in multiprocessor systems that have a need to communicate in real time and Fully asynchronous operation from each of the four ports: also offers added benefit for high-speed systems in which multiple access P1, P2, P3, P4 is required in the same cycle. Versatile control for write-inhibit: separate BUSY input to The IDT7052 is also designed to be used in systems where on-chip control write-inhibit for each of the four ports hardware port arbitration is not needed. This part lends itself to those Functional Block Diagram R/WP1 R/WP4 CEP4 CEP1 OEP1 OEP4 COLUMN COLUMN I/O0P1-I/O7P1 I/O0P4-I/O7P4 I/O I/O BUSYP1 BUSYP4 PORT 1 PORT 4 ADDRESS ADDRESS A0P1-A10P1 A0P4-A10P4 DECODE DECODE LOGIC LOGIC MEMORY ARRAY PORT 2 PORT 3 ADDRESS ADDRESS A0P2-A10P2 A0P3-A10P3 DECODE DECODE LOGIC LOGIC BUSYP2 BUSYP3 COLUMN COLUMN I/O0P2-I/O7P2 I/O0P3-I/O7P3 I/O I/O OEP2 OEP3 CEP2 CEP3 R/WP3 R/WP2 2674 drw 01 JULY 2019 1 DSC 2674/177052S/L High-Speed 2K x 8 FourPort Static RAM Military, Industrial and Commercial Temperature Ranges systems which cannot tolerate wait states or are designed to be able to Fabricated using CMOS high-performance technology, this FourPort externally arbitrate or withstand contention when all ports simultaneously SRAM typically operates on only 750mW of power. Low-power (L) access the same FourPort RAM location. versions offer battery backup data retention capability, with each port The IDT7052 provides four independent ports with separate control, typically consuming 50W from a 2V battery. address, and I/O pins that permit independent, asynchronous access for The IDT7052 is packaged in a ceramic 108-pin Pin Grid Array (PGA) reads or writes to any location in memory. It is the users responsibility to and 120-pin Thin Quad Flatpack (TQFP). Military grade product is ensure data integrity when simultaneously accessing the same memory manufactured in compliance with the latest revision of MIL-PRF-38535 location from all ports. An automatic power down feature, controlled by CE, QML, making it ideally suited to military temperature applications de- permits the on-chip circuitry of each port to enter a very low power standby manding the highest level of performance and reliability. power mode. (1,2,3) Pin Configurations 81 80 77 74 72 69 68 65 63 60 57 54 R/W NC A7 A5 A3 A0 A0 A3 A5 A7 NC R/W 12 P2 P2 P2 P2 P2 P3 P3 P3 P3 P3 84 83 78 76 73 70 67 64 61 59 56 53 BUSY 11 OE A8 A10 A4 A1 A1 A4 A10 A8 OE BUSY P2 P2 P2 P2 P2 P2 P3 P3 P3 P3 P3 P3 87 86 82 79 75 71 66 62 58 55 51 50 CE A2 A1 A9 A6 A2 A2 A6 A9 CE A1 A2 10 P1 P1 P2 P2 P2 P3 P3 P3 P3 P4 P4 90 88 85 52 49 47 A5 A3 A0 09 A0 A3 A5 P1 P1 P1 P4 P4 P4 92 91 89 48 46 45 A6 A4 A4 A6 A10 A10 08 P1 P1 P4 P4 P4 P1 95 94 93 44 43 42 8 A8 A7 GND A 7 A 07 VCC IDT7052G P4 P4 P1 P1 (4) GU108 96 97 98 39 40 41 CE A 9 A9 CE NC NC 108-Pin PGA 06 P4 P4 P1 P1 (5) Top View 99 100 102 35 37 38 OE 05 R/W OE I/O0 GND R/W P4 P4 P1 P1 P1 101 103 106 31 34 36 BUSY 7 BUSY 04 I/O1 GND GND I/O P1 P4 P4 P1 104 105 1 4 8 12 17 21 25 28 32 33 I/O2 I/O3 I/O6 I/O2 I/O5 I/O6 03 GND VCC VCC GND VCC VCC P1 P1 P1 P4 P4 P4 107 2 5 7 10 13 16 19 22 24 29 30 I/O4 I/O7 I/O0 02 I/O2 I/O4 I/O6 I/O1 I/O3 I/O5 I/O7 I/O3 I/O4 P1 P1 P2 P2 P2 P2 P3 P3 P3 P3 P4 P4 108 3 6 9 11 14 15 18 20 23 26 27 I/O5 NC I/O1 I/O3 I/O5 I/O7 I/O0 I/O2 I/O4 I/O6 I/O0 I/O1 01 P1 P2 P2 P2 P2 P3 P3 P3 P3 P4 P4 , A B C D E F G H J K L M 2674 drw 02 INDEX NOTES: 1. All VCC pins must be connected to the power supply. 2. All GND pins must be connected to the ground supply. 3. Package body is approximately 1.21 in x 1.21 in x .16 in. 4. This package code is used to reference the package diagram. 5. This text does not indicate orientation of the actual part-marking. 2 6.42