Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as Cypress document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.comCY7C1041GN 4-Mbit (256K words 16 bit) Static RAM 4-Mbit (256K words 16 bit) Static RAM Data writes are performed by asserting the Chip Enable (CE) and Features Write Enable (WE) inputs LOW, while providing the data on I/O 0 High speed through I/O and address on A through A pins. The Byte High 15 0 17 t = 10 ns / 15 ns Enable (BHE) and Byte Low Enable (BLE) inputs control write AA operations to the upper and lower bytes of the specified memory Low active and standby currents location. BHE controls I/O through I/O and BLE controls I/O 8 15 0 Active current: I = 38-mA typical CC through I/O . 7 Standby current: I = 6-mA typical SB2 Data reads are performed by asserting the Chip Enable (CE) and Operating voltage range: 1.65 V to 2.2 V, 2.2 V to 3.6 V, and Output Enable (OE) inputs LOW and providing the required 4.5 V to 5.5 V address on the address lines. Read data is accessible on the I/O 1.0-V data retention lines (I/O through I/O ). Byte accesses can be performed by 0 15 asserting the required byte enable signal (BHE or BLE) to read TTL-compatible inputs and outputs either the upper byte or the lower byte of data from the specified address location. Pb-free 44-pin SOJ, 44-pin TSOP II, and 48-ball VFBGA packages All I/Os (I/O through I/O ) are placed in a high-impedance state 0 15 during the following events: Functional Description The device is deselected (CE HIGH) CY7C1041GN is high-performance CMOS fast static RAM The control signals (OE, BLE, BHE) are de-asserted Organized as 256K words by 16-bits. The logic block diagram is on page 2. Product Portfolio Power Dissipation Speed Operating I , (mA) (ns) CC Product Range V Range (V) Standby, I (mA) CC SB2 f = f max 10/15 1 1 Typ Max Typ Max CY7C1041GN18 1.65 V2.2 V 15 40 CY7C1041GN30 Industrial 2.2 V3.6 V 10 38 45 68 CY7C1041GN 4.5 V5.5 V 10 38 45 Notes 1. Typical values are included only for reference and are not guaranteed or tested. Typical values are measured at V = 1.8 V (for a V range of 1.65 V2.2 V), CC CC V = 3 V (for a V range of 2.2 V3.6 V), and V = 5 V (for a V range of 4.5 V5.5 V), T = 25 C. CC CC CC CC A Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-95413 Rev. *D Revised September 9, 2016