HIGH-SPEED 32/16K x 18 709379 SYNCHRONOUS PIPELINED *709369 DUAL-PORT STATIC RAM *SPECIFIED PART IS OBSOLETE NOT RECOMMENDED FOR NEW DESIGNS Features True Dual-Ported memory cells which allow simultaneous Full synchronous operation on both ports access of the same memory location 4ns setup to clock and 0ns hold on all control, data, and High-speed clock to data access address inputs Commercial: 7.5/9/12ns (max.) Data input, address, and control registers Insustrial: 9ns (max.) Fast 7.5ns clock to data out in the Pipelined output mode Low-power operation Self-timed write allows fast cycle time IDT709379/69L 10ns cycle time, 100MHz operation in Pipelined output mode Active: 1.2W (typ.) Separate upper-byte and lower-byte controls for Standby: 2.5mW (typ.) multiplexed bus and bus matching compatibility Flow-Through or Pipelined output mode on either Port via TTL- compatible, single 5V (10%) power supply the FT/PIPE pins Industrial temperature range (40C to +85C) is Counter enable and reset features available for selected speeds Dual chip enables allow for depth expansion without Available in a 100-pin Thin Quad Flatpack (TQFP) package additional logic Green parts available, see ordering information Note that information regarding recently obsoleted parts is included in this datasheet for customer convenience. Functional Block Diagram R/WL R/WR UBL UBR CE0L CE0R 1 1 CE1L CE1R 0 0 0/1 0/1 LBL LBR OEL OER 1b 0b 1a 0a 0a 1a 0b 1b FT/PIPEL 0/1 ba ab 0/1 FT/PIPER I/O9L-I/O17L I/O9R-I/O17R I/O I/O Control Control I/O0L-I/O8L I/O0R-I/O8R (1) (1) A14L A14R Counter/ Counter/ MEMORY A0R A0L Address Address CLKR CLKL ARRAY Reg. Reg. ADSR ADSL CNTENR CNTENL CNTRSTL CNTRSTR 4845 drw 01 NOTE: 1. A14X is a NC for IDT709369. FEBRUARY 2018 1 DSC-4845/8 2018 Integrated Device Technology, Inc.709379/69L High-Speed 32/16K x 18 Synchronous Pipelined Dual-Port Static RAM Industrial and Commercial Temperature Ranges Description The IDT709379/69 is a high-speed 32/16K x 18 bit synchronous With an input data register, the IDT709379/69 has been optimized for applications having unidirectional or bidirectional data flow in bursts. Dual-Port RAM. The memory array utilizes Dual-Port memory cells to An automatic power down feature, controlled by CE0 and CE1, permits allow simultaneous access of any address from both ports. Registers on control, data, and address inputs provide minimal setup and hold the on-chip circuitry of each port to enter a very low standby power times. The timing latitude provided by this approach allows systems mode. Fabricated using CMOS high-performance technology, these devices typically operate on only 1.2W of power. to be designed with very short cycle times. (1,2,3) Pin Configurations INDEX 10099 98 97 9695 9493 92 9190 8988 87 86 85 84 838281 80 79 7877 76 A9L 1 A8R 75 A10L 2 A9R 74 A10R A11L 3 73 A11R A12L 4 72 A13L A12R 5 71 (1) A14L A13R 6 70 (1) A14R NC 7 69 NC LBL 8 68 UBL 9 67 LBR 10 CE0L 66 UBR 709379/69PF 11 CE1L 65 CE0R (5) PN100 CNTRSTL 12 64 CE1R 13 R/WL 63 CNTRSTR 100-Pin TQFP R/WR OEL 14 62 (6) VCC GND 15 61 Top View FT/PIPEL 16 60 OER . I/O17L 17 59 FT/PIPER I/O16L 18 58 I/O17R GND 19 GND 57 I/O15L 20 56 I/O16R I/O14L 21 55 I/O15R I/O13L 22 54 I/O14R I/O12L 23 53 I/O13R I/O11L 24 52 I/O12R I/O10L 25 51 I/O11R 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 4845 drw 02 NOTES: 1. A14x is a NC for IDT709369. 2. All VCC pins must be connected to power supply. 3. All GND pins must be connected to ground. 4. Package body is approximately 14mm x 14mm x 1.4mm 5. This package code is used to reference the package diagram. 6. This text does not indicate orientation of the actual part-marking. 6.422 A8L I/O9L A7L I/O8L A6L CC V A5L I/O7L A4L I/O6L A3L I/O5L A2L I/O4L A1L I/O3L A0L I/O2L CNTENL GND I/O1L CLKL I/O0L ADSL GND GND GND I/O0R ADSR I/O1R CLKR I/O2R I/O3R CNTENR A0R I/O4R A1R I/O5R A2R /O6R I A3R VCC A4R I/O7R A5R I/O8R A6R I/O9R A7R I/O10R