CY7C1061G30-10ZXE Infineon

CY7C1061G Automotive 16-Mbit (1 M words 16 bit) Static RAM with Error-Correcting Code (ECC) 16-Mbit (1 M words 16 bit) Static RAM with Error-Correcting Code (ECC) Features Functional Description 1 High speed CY7C1061G is a high-performance CMOS fast static RAM automotive part with embedded ECC. ECC logic can detect and t = 10 ns AA correct single-bit error in read data word during read cycles. Temperature range This device has single chip enable input and is accessed by Automotive-E: 40 C to 125 C asserting the chip enable input (CE) LOW. Embedded error-correcting code (ECC) for single-bit error To perform data writes, assert the Write Enable (WE) input LOW correction and provide the data and address on the device data pins (I/O 0 through I/O ) and address pins (A through A ) respectively. Low active and standby currents 15 0 19 The Byte High Enable (BHE) and Byte Low Enable (BLE), inputs I = 90-mA typical at 100 MHz CC control byte writes and write data on the corresponding I/O lines I = 20-mA typical SB2 to the memory location specified. BHE controls I/O through 8 Operating voltage range: 2.2 V to 3.6 V I/O and BLE controls I/O through I/O . 15 0 7 1.0-V data retention To perform data reads, assert the Output Enable (OE) input and provide the required address on the address lines. Read data is Transistor-transistor logic (TTL) compatible inputs and outputs accessible on I/O lines (I/O through I/O ). You can perform 0 15 Available in Pb-free 48-ball VFBGA and 48-pin TSOPI byte accesses by asserting the required byte enable signal (BHE packages or BLE) to read either the upper byte or the lower byte of data from the specified address location. through I/O ) are placed in a high-impedance state All I/Os (I/O 0 15 when the device is deselected (CE HIGH), or control signals are , BLE, BHE). Refer to the below logic block de-asserted (OE diagram. The CY7C1061G automotive device is available in 48-ball VFBGA and 48-pin TSOP I packages. Logic Block Diagram CY7C1061G ECC ENCODER INPUT BUFFER A0 A1 A2 A3 I/O I/O 0 7 MEMORY A4 ARRAY A5 I/O I/O 8 15 A6 A7 A8 A9 COLUMN DECODER BHE WE CE OE BLE Note 1. The device does not support automatic write-back on error detection. Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-84821 Rev. *I Revised September 13, 2016 ROWDECODER A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 SENSE AMPLIFIERS ECCDECODERCY7C1061G Automotive Contents Pin Configurations ...........................................................3 Ordering Information ...................................................... 13 Product Portfolio ..............................................................3 Ordering Code Definitions ......................................... 13 Maximum Ratings .............................................................4 Package Diagrams .......................................................... 14 Operating Range ...............................................................4 Acronyms ........................................................................15 DC Electrical Characteristics ..........................................4 Document Conventions ................................................. 15 Capacitance ......................................................................5 Units of Measure ....................................................... 15 Thermal Resistance ..........................................................5 Document History Page ................................................. 16 AC Test Loads and Waveforms .......................................5 Sales, Solutions, and Legal Information ...................... 18 Data Retention Characteristics .......................................6 Worldwide Sales and Design Support ....................... 18 Data Retention Waveform ................................................6 Products ....................................................................18 AC Switching Characteristics .........................................7 PSoC Solutions ...................................................... 18 Switching Waveforms ......................................................8 Cypress Developer Community ................................. 18 Truth Table ......................................................................12 Technical Support ..................................................... 18 Document Number: 001-84821 Rev. *I Page 2 of 18