HIGH SPEED 71321SA/LA 2K X 8 DUAL-PORT 71421SA/LA STATIC RAM WITH INTERRUPTS Features MASTER IDT71321 easily expands data bus width to 16-or- High-speed access more-bits using SLAVE IDT71421 Commercial: 20/35/55ns (max.) On-chip port arbitration logic (IDT71321 only) Industrial: 25/55ns (max.) BUSY output flag on IDT71321 BUSY input on IDT71421 Low-power operation Fully asynchronous operation from either port IDT71321/IDT71421SA Battery backup operation 2V data retention (LA only) Active: 325mW (typ.) TTL-compatible, single 5V 10% power supply Standby: 5mW (typ.) Available in 52-Pin PLCC, 52-Pin STQFP, 64-Pin TQFP, and IDT71321/421LA 64-Pin STQFP Active: 325mW (typ.) Industrial temperature range (40C to +85C) is available Standby: 1mW (typ.) for selected speeds Two INT flags for port-to-port communications Green parts available, see ordering information Functional Block Diagram OEL OER CEL CER R/WL R/WR I/O0L- I/O7L I/O0R-I/O7R I/O I/O Control Control (1,2) (1,2) BUSYL BUSYR A10L A10R Address MEMORY Address Decoder ARRAY Decoder A0L A0R 11 11 ARBITRATION CEL CER and INTERRUPT OER OEL LOGIC R/WR R/WL (2) (2) INTR INTL 2691 drw 01 NOTES: 1. IDT71321 (MASTER): BUSY is open drain output and requires pullup resistor of 270. IDT71421 (SLAVE): BUSY is input. 2. Open drain output: requires pullup resistor of 270. SEPTEMBER 2019 1 2019 Integrated Device Technology, Inc. DSC-2691/1771321SA/LA and 71421SA/LA High Speed 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges Description The IDT71321/IDT71421 are high-speed 2K x 8 Dual-Port Static address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. An automatic power RAMs with internal interrupt logic for interprocessor communications. The IDT71321 is designed to be used as a stand-alone 8-bit Dual- down feature, controlled by CE, permits the on chip circuitry of each port to enter a very low standby power mode. Port Static RAM or as aMASTE Dual-Port Static RAM together Fabricated using CMOS high-performance technology, these de- with the IDT71421SLAV Dual-Port in 16-bit-or-more word width vices typically operate on only 325mW of power. Low-power (LA) systems. Using the IDT MASTER/SLAVE Dual-Port Static RAM ap- proach in 16-or-more-bit memory system applications results in full versions offer battery backup data retention capability, with each Dual- Port typically consuming 200W from a 2V battery. speed, error-free operation without the need for additional discrete The IDT71321/IDT71421 devices are packaged in 52-pin PLCC, logic. 52-pin STQFP, 64-pin TQFP, and 64-pin STQFP. Both devices provide two independent ports with separate control, (1,2,3) Pin Configurations 20 19 18 17 16 15 14 13 12 11 10 9 8 I/O 4L 21 7 A 0L 6 I/O 5L 22 OEL I/O 23 5 A 10L 6L 4 I/O 7L 24 INTL NC 3 BUSYL 25 GND 26 2 R/WL 0R I/O 1 CEL 27 71321/421 (4) PLG52 52 1R 28 V CC I/O PLCC 2R 29 51 I/O CER Top View 50 I/O 3R 30 R/W R I/O 4R 49 BUSYR 31 I/O 5R 32 48 INTR 47 33 A 10R I/O 6R 34 35 36 37 38 39 40 41 42 43 44 45 46 2691 drw 02 484746 45444342414039 38 3736 3534 33 32 N/C 49 I/O5R N/C 50 31 I/O4R A10R 51 30 N/C INTR 52 29 I/O3R BUSYR 53 28 I/O2R R/WR 54 27 I/O1R CER 55 26 71321/421 I/O0R (4) VCC 56 PNG64/PPG64 25 GND VCC 24 GND 57 64-Pin TQFP CEL 58 23 N/C 64-Pin STQFP R/WL 59 22 I/O7L Top View BUSYL 60 21 I/O6L 61 INTL 20 I/O5L NOTES: A10L 62 19 I/O4L 1. All VCC pins must be connected to power supply. N/C 63 18 N/C 2. All GND pins must be connected to ground supply. N/C 64 17 I/O3L 3. PLG52 package body is approximately .75 in x .75 in x .17 in. 10 111213 14 1516 1 2 3 4 5 6 7 8 9 PNG64 package body is approximately 14mm x 14mm x 1.4mm. PPG64 package body is approximately 10mm x 10mm x 1.4mm. 2691 drw 03 4. This package code is used to reference the package diagram. 6.422 I/O 7R 3L I/O NC I/O 2L 9R A I/O 1L A 8R I/O 0L 7R A A 9L A 6R 8L A 5R A 7L A A 4R A 6L 3R A 5L A A 2R 4L A A 1R A 3L 0R A A 2L OE R A 1L OEL OER A0L A0R A1R A1L A2R A2L A3R A3L A4R A4L A5R A5L A6R A6L N/C N/C A7R A7L A8R A8L A9R A9L N/C N/C N/C I/O0L I/O7R I/O1L I/O2L I/O6R