Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as Cypress document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.comCY7C1441KV33 CY7C1443KV33 CY7C1441KVE33 36-Mbit (1M 36/2M 18) Flow-Through SRAM (With ECC) 36-Mbit (1M 36/2M 18) Flow-Through SRAM (With ECC) Features Functional Description Supports 133-MHz bus operations The CY7C1441KV33/CY7C1443KV33/CY7C1441KVE33 are 3.3 V, 1M 36/2M 18/1M 36 synchronous flow-through 1M 36/2M 18 common I/O SRAMs, respectively designed to interface with high-speed 3.3 V core power supply microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133 MHz version). A 2-bit on-chip 2.5 V or 3.3 V I/O power supply counter captures the first address in a burst and increments the Fast clock-to-output times address automatically for the rest of the burst access. All 6.5 ns (133 MHz version) synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock (CLK) input. The synchronous Provide high-performance 2-1-1-1 access rate inputs include all addresses, all data inputs, address-pipelining User-selectable burst counter supporting Intel Pentium Chip Enable (CE ), depth-expansion Chip Enables (CE and 1 2 interleaved or linear burst sequences CE ), Burst Control inputs (ADSC, ADSP, and ADV), Write 3 Enables (BW , and BWE), and Global Write (GW). Separate processor and controller address strobes x Asynchronous inputs include the Output Enable (OE) and the ZZ Synchronous self-timed write pin. Asynchronous output enable CY7C1441KVE33 The CY7C1441KV33/CY7C1443KV33/ allow CY7C1441KV33, CY7C1443KV33, and CY7C1441KVE33 are either interleaved or linear burst sequences, selected by the available in JEDEC-standard 100-pin TQFP and 165-ball MODE input pin. A HIGH selects an interleaved burst sequence, FBGA Pb-free packages. while a LOW selects a linear burst sequence. Burst accesses can be initiated with the Processor Address Strobe (ADSP) or the IEEE 1149.1 JTAG-Compatible Boundary Scan cache Controller Address Strobe (ADSC) inputs. Address ZZ Sleep Mode option advancement is controlled by the Address Advancement (ADV) input. On-chip error correction code (ECC) to reduce soft error rate (SER) Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor (ADSP) or Address Strobe Controller (ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin (ADV). The CY7C1441KV33/CY7C1443KV33/CY7C1441KVE33 operate from a +3.3 V core power supply while all outputs may operate with either a +2.5 V or +3.3 V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible. Selection Guide Description 133 MHz Unit Maximum access time 6.5 ns Maximum operating current 18 150 mA 36 170 Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-66677 Rev. *J Revised December 5, 2019