Clk 512K x 36, 1M x 18 IDT71T75602 2.5V Synchronous ZBT SRAMs IDT71T75802 2.5V I/O, Burst Counter Pipelined Outputs Features 512K x 36, 1M x 18 memory configurations 4-word burst capability (interleaved or linear) Supports high performance system speed - 200 MHz Individual byte write (BW1 - BW4) control (May tie active) (3.2 ns Clock-to-Data Access) Three chip enables for simple depth expansion TM ZBT Feature - No dead cycles between write and read 2.5V power supply (5%) cycles 2.5V I/O Supply (VDDQ) Internally synchronized output buffer enable eliminates the Power down controlled by ZZ input need to control OE Boundary Scan JTAG Interface (IEEE 1149.1 Compliant) Single R/W (READ/WRITE) control pin Packaged in a JEDEC standard 100-pin plastic thin quad Positive clock-edge triggered address, data, and control flatpack (TQFP), 119 ball grid array (BGA) signal registers for fully pipelined applications Green parts available, see Ordering Information Functional Block Diagram - 512K x 36 LBO 512Kx36 BIT MEMORY ARRAY Address A 0:18 DQ Address CE1, CE2, CE2 R/W DQ Control CEN ADV/LD DI DO BWx DQ Control Logic Clk Mux Sel D Clock Output Register Q Gate OE TMS Data I/O 0:31 , TDI JTAG TDO I/O P 1:4 TCK TRST 5313 drw 01 (optional) OCTOBER 2017 1 2017 Integrated Device Technology, Inc. DSC-5313/11 Input RegisterClk IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges 1, CE2, CE2) that allow the user There are three chip enable pins (CE Description to deselect the device when desired. If any one of these three is not The IDT71T75602/802 are 2.5V high-speed 18,874,368-bit (18 Mega- asserted when ADV/LD is low, no new memory operation can be initiated. bit) synchronous SRAMs. They are designed to eliminate dead bus However, any pending data transfers (reads or writes) will be com- cycles when turning the bus around between reads and writes, or writes pleted. The data bus will tri-state two cycles after the chip is deselected or TM and reads. Thus, they have been given the name ZBT , or Zero Bus a write is initiated. Turnaround. The IDT71T75602/802 have an on-chip burst counter. In the burst Address and control signals are applied to the SRAM during one clock mode, the IDT71T75602/802 can provide four cycles of data for a single cycle, and two cycles later the associated data cycle occurs, be it read or address presented to the SRAM. The order of the burst sequence is write. defined by the LBO input pin. The LBO pin selects between linear and The IDT71T75602/802 contain data I/O, address and control signal interleaved burst sequence. The ADV/LD signal is used to load a new registers. Output enable is the only asynchronous signal and can be used external address (ADV/LD = LOW) or increment the internal burst to disable the outputs at any given time. counter (ADV/LD = HIGH). A Clock Enable CEN pin allows operation of the IDT71T75602/802 The IDT71T75602/802 SRAMs utilize a high-performance 2.5V to be suspended as long as necessary. All synchronous inputs are CMOS process, and are packaged in a JEDEC Standard 14mm x ignored when (CEN) is high and the internal device registers will hold their 20mm 100pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid previous values. array (BGA). Functional Block Diagram - 1M x 18 LBO 1Mx18 BIT MEMORY ARRAY Address A 0:19 DQ Address CE1, CE2, CE2 R/W DQ Control CEN ADV/LD DI DO BWx DQ Control Logic Clk Mux Sel D Clock Output Register Q Gate OE TMS TDI Data I/O 0:15 , JTAG TDO TCK I/O P 1:2 TRST 5313 drw 01b (optional) 6.422 Input Register