Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as Cypress document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.comCY7C2245KV18 36-Mbit QDR II+ SRAM Four-Word Burst Architecture (2.0 Cycle Read Latency) with ODT 36-Mbit QDR II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Features Configurations Separate independent read and write data ports With Read Cycle Latency of 2.0 Cycles: Supports concurrent transactions CY7C2245KV18 1M 36 450 MHz clock for high bandwidth Functional Description Four-word burst for reducing address bus frequency The CY7C2245KV18 is 1.8 V synchronous pipelined SRAM, Double data rate (DDR) interfaces on both read and write ports equipped with QDR II+ architecture. Similar to QDR II (data transferred at 900 MHz) at 450 MHz architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The Available in 2.0 clock cycle latency read port has dedicated data outputs to support read operations Two input clocks (K and K) for precise DDR timing and the write port has dedicated data inputs to support write SRAM uses rising edges only operations. QDR II+ architecture has separate data inputs and data outputs to completely eliminate the need to turn-around Echo clocks (CQ and CQ) simplify data capture in high speed the data bus that exists with common I/O devices. Each port is systems accessed through a common address bus. Addresses for read and write addresses are latched on alternate rising edges of the Data valid pin (QVLD) to indicate valid data on the output input (K) clock. Accesses to the QDR II+ read and write ports are On-die termination (ODT) feature completely independent of one another. To maximize data Supported for D , BWS , and K/K inputs throughput, both read and write ports are equipped with DDR x:0 x:0 interfaces. Each address location is associated with four 36-bit Single multiplexed address input bus latches address inputs words (CY7C2245KV18) that burst sequentially into or out of the for read and write ports device. Because data is transferred into and out of the device on Separate port selects for depth expansion every rising edge of both input clocks (K and K), memory bandwidth is maximized while simplifying system design by Synchronous internally self-timed writes eliminating bus turn-arounds. QDR II+ operates with 2.0 cycle read latency when DOFF is These devices have an on-die termination feature supported for asserted HIGH D , BWS , and K/K inputs, which helps eliminate external x:0 x:0 termination resistors, reduce cost, reduce board area, and Operates similar to QDR I device with 1 cycle read latency when simplify board routing. DOFF is asserted LOW Depth expansion is accomplished with port selects, which Available in 36 configurations enables each port to operate independently. Full data coherency, providing most current data All synchronous inputs pass through input registers controlled by 1 the K or K input clocks. All data outputs pass through output Core V = 1.8 V 0.1 V I/O V = 1.4 V to V DD DDQ DD registers controlled by the K or K input clocks. Writes are Supports both 1.5 V and 1.8 V I/O supply conducted with on-chip synchronous self-timed write circuitry. HSTL inputs and variable drive HSTL output buffers For a complete list of related documentation, click here. Available in 165-ball FBGA package (13 15 1.4 mm) Offered in Pb-free packages JTAG 1149.1 compatible test access port Phase-locked loop (PLL) for accurate data placement Selection Guide Description 450 MHz Unit Maximum operating frequency 450 MHz Maximum operating current 36 1020 mA Note 1. The Cypress QDR II+ devices surpass the QDR consortium specification and can support V = 1.4 V to V . DDQ DD Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-87885 Rev. *D Revised January 4, 2018