256K x 36, 512K x 18 IDT71V65703 3.3V Synchronous ZBT SRAMs IDT71V65903 3.3V I/O, Burst Counter Flow-Through Outputs Features Address and control signals are applied to the SRAM during one clock cycle, and on the next clock cycle the associated data cycle 256K x 36, 512K x 18 memory configurations occurs, be it read or write. Supports high performance system speed - 100 MHz The IDT71V65703/5903 contain address, data-in and control (7.5 ns Clock-to-Data Access) TM signal registers. The outputs are flow-through (no output data ZBT Feature - No dead cycles between write and read register). Output enable is the only asynchronous signal and can be cycles used to disable the outputs at any given time. Internally synchronized output buffer enable eliminates the A Clock Enable (CEN) pin allows operation of the IDT71V65703/5903 need to control OE to be suspended as long as necessary. All synchronous inputs are ignored when Single R/W (READ/WRITE) control pin CEN is high and the internal device registers will hold their previous values. 4-word burst capability (Interleaved or linear) There are three chip enable pins (CE1, CE2, CE2) that allow the Individual byte write (BW1 - BW4) control (May tie active) user to deselect the device when desired. If any one of these three Three chip enables for simple depth expansion is not asserted when ADV/LD is low, no new memory operation can 3.3V power supply (5%) be initiated. However, any pending data transfers (reads or writes) 3.3V (5%) I/O Supply (VDDQ) will be completed. The data bus will tri-state one cycle after the chip Power down controlled by ZZ input is deselected or a write is initiated. Packaged in a JEDEC standard 100-pin plastic thin quad The IDT71V65703/5903 have an on-chip burst counter. In the burst flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch mode, the IDT71V65703/5903 can provide four cycles of data for a single ball grid array (fBGA) address presented to the SRAM. The order of the burst sequence is Green parts available, see ordering information defined by the LBO input pin. The LBO pin selects between linear and interleaved burst sequence. The ADV/LD signal is used to load a new Description external address (ADV/LD = LOW) or increment the internal burst counter The IDT71V65703/5903 are 3.3V high-speed 9,437,184-bit (ADV/LD = HIGH). (9 Megabit) synchronous SRAMs organized as 256K x 36 / 512K x 18. The IDT71V65703/5903 SRAMs utilize a high-performance CMOS They are designed to eliminate dead bus cycles when turning the bus process and are packaged in a JEDEC Standard 14mm x 20mm 100- around between reads and writes, or writes and reads. Thus they have pin plastic thin quad flatpack (TQFP), 119 ball grid array (BGA) and a 165 TM been given the name ZBT , or Zero Bus Turnaround. fine pitch ball grid array (fBGA). Pin Description Summary A0-A 18 Address Inputs Input Synchronous Chip Enables Input Synchronous CE1, CE2, CE2 OE Output Enable Input Asynchronous R/W Read/Write Signal Input Synchronous Clock Enable Input Synchronous CEN BW1, BW2, BW3, BW4 Individual Byte Write Selects Input Synchronous CLK Clock Input N/A ADV/LD Advance Burst Address/Load New Address Input Synchronous LBO Linear/Interleaved Burst Order Input Static ZZ Sleep Mode Input Asynchronous I/O0-I/O31, I/OP1-I/OP4 Data Input/Output I/O Synchronous VDD, VDDQ Core Power, I/O Power Supply Static VSS Ground Supply Static 5298 tbl 01 ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola, Inc. OCTOBER 2014 1 2014 Integrated Device Technology, Inc. DSC-5298/05IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBT SRAMs with 3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges (1) Pin Definitions Symbol Pin Function I/O Active Description A0-A18 Address Inputs I N/A Synchronous Address inputs. The address register is triggered by a combination of the rising edge of CLK, ADV/LD low, CEN low, and true chip enables. ADV/LD Advance / Load I N/A ADV/LD is a synchronous input that is used to load the internal registers with new address and control when it is sampled low at the rising edge of clock with the chip selected. When ADV/LD is low with the chip deselected, any burst in progress is terminated. When ADV/LD is sampled high then the internal burst counter is advanced for any burst that was in progress. The external addresses are ignored when ADV/LD is sampled high. R/W Read / Write I N/A R/W signal is a synchronous input that identifies whether the current load cycle initiated is a Read or Write access to the memory array. The data bus activity for the current cycle takes place one clock cycle later. Clock Enable I LOW Synchronous Clock Enable Input. When CEN is sampled high, all other synchronous inputs, including CEN clock are ignored and outputs remain unchanged. The effect of CEN sampled high on the device outputs is as if the low to high clock transition did not occur. For normal operation, CEN must be sampled low at rising edge of clock. Individual Byte I LOW Synchronous byte write enables. Each 9-bit byte has its own active low byte write enable. On load BW1-BW4 Write Enables write cycles (When R/W and ADV/LD are sampled low) the appropriate byte write signal (BW1-BW4) must be valid. The byte write signal must also be valid on each cycle of a burst write. Byte Write signals are ignored when R/W is sampled high. The appropriate byte(s) of data are written into the device one cycle later. BW1-BW4 can all be tied low if always doing write to the entire 36-bit word. Chip Enables I LOW Synchronous active low chip enable. CE1 and CE2 are used with CE2 to enable the IDT71V65703/5903 CE1, CE2 (CE1 or CE2 sampled high or CE2 sampled low) and ADV/LD low at the rising edge of clock, initiates TM a deselect cycle. The ZBT has a one cycle deselect, i.e., the data bus will tri-state one clock cycle after deselect is initiated. CE2 Chip Enable I HIGH Synchronous active high chip enable. CE2 is used with CE1 and CE2 to enable the chip. CE2 has inverted polarity but otherwise identical to CE1 and CE2. CLK Clock I N/A This is the clock input to the IDT71V65703/5903. Except for OE, all timing references for the device are made with respect to the rising edge of CLK. I/O0-I/O31 Data Input/Output I/O N/A Data input/output (I/O) pins. The data input path is registered, triggered by the rising edge of CLK. The I/OP1-I/OP4 data output path is flow-through (no output register). LBO Linear Burst I LOW Burst order selection input. When LBO is high the Interleaved burst sequence is selected. When LBO Order is low the Linear burst sequence is selected. LBO is a static input, and it must not change during device operation. OE Output Enable I LOW Asynchronous output enable. OE must be low to read data from the 71V65703/5903. When OE is HIGH the I/O pins are in a high-impedance state. OE does not need to be actively controlled for read and write cycles. In normal operation, OE can be tied low. ZZ Sleep Mode I HIGH Asynchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down the IDT71V65703/5903 to its lowest power consumption level. Data retention is guaranteed in Sleep Mode. VDD Power Supply N/A N/A 3.3V core power supply. VDDQ Power Supply N/A N/A 3.3V I/O supply. VSS Ground N/A N/A Ground. 5298 tbl 02 NOTE: 1. All synchronous inputs must meet specified setup and hold times with respect to CLK. 6.422