71V67703 256K X 36, 512K X 18 71V67903 3.3V Synchronous SRAMs 3.3V I/O, Burst Counter Flow-Through Outputs, Single Cycle Deselect Features 3.3V core power supply 256K x 36, 512K x 18 memory configurations Power down controlled by ZZ input Supports fast access times: 3.3V I/O supply (VDDQ) 7.5ns up to 117MHz clock frequency Packaged in a JEDEC Standard 100-pin thin plastic quad 8.0ns up to 100MHz clock frequency flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch ball 8.5ns up to 87MHz clock frequency grid array (fBGA) LBO input selects interleaved or linear burst mode Industrial temperature range (40C to +85C) is available Self-timed write cycle with global write control (GW), byte write for selected speeds enable (BWE), and byte writes (BWx) Green parts available, see ordering information Functional Block Diagram LBO ADV INTERNAL Burst ADDRESS CEN Sequence 256K x 36/ CLK 2 Burst 18/19 Binary 512K x 18- Logic Counter ADSC A0* BIT Q0 MEMORY CLR A1* ARRAY Q1 ADSP 2 CLK EN A0,A1 A2- A18 ADDRESS A0A17/18 36/18 REGISTER 36/18 18/19 GW BWE Byte 1 Write Register Byte 1 Write Driver BW1 9 Byte 2 Write Register Byte 2 Write Driver BW2 9 Byte 3 Write Register Byte 3 Write Driver BW3 9 Byte 4 Byte 4 Write Register Write Driver BW4 9 CE Q D CS0 Enable DATA INPUT CS1 Register REGISTER CLK EN ZZ Powerdown OE OUTPUT BUFFER OE , 36/18 I/O0I/O31 I/OP1I/OP4 5309 drw 01 1 Aug.11.2171V67703, 71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Flow-Through Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges Description initiating the access sequence. The first cycle of output data will flow- The IDT71V67703/7903 are high-speed SRAMs organized as 256K through from the array after a clock-to-data access time delay from the x 36/512K x 18. The IDT71V67703/7903 SRAMs contain write, data, rising clock edge of the same cycle. If burst mode operation is selected address and control registers. There are no registers in the data output (ADV=LOW), the subsequent three cycles of output data will be available path (flow-through architecture). Internal logic allows the SRAM to to the user on the next three rising clock edges. The order of these three generate a self-timed write based upon a decision which can be left until addresses are defined by the internal burst counter and the LBO input pin. the end of the write cycle. The IDT71V67703/7903 SRAMs utilize a high-performance CMOS The burst mode feature offers the highest level of performance to the process and are packaged in a JEDEC standard 14mm x 20mm 100-pin system designer, as the IDT71V67703/7903 can provide four cycles of thin plastic quad flatpack (TQFP) as well as a 119 ball grid array (BGA) data for a single address presented to the SRAM. An internal burst and a 165 fine pitch ball grid array (fBGA). address counter accepts the first cycle address from the processor, Pin Description Summary A0-A18 Address Inputs Input Synchronous Chip Enable Input Synchronous CE CS0, CS1 Chip Selects Input Synchronous Output Enable Input Asynchronous OE Global Write Enable Input Synchronous GW Byte Write Enable Input Synchronous BWE (1) Individual Byte Write Selects Input Synchronous BW1, BW2, BW3, BW4 CLK Clock Input N/A Burst Address Advance Input Synchronous ADV Address Status (Cache Controller) Input Synchronous ADSC ADSP Address Status (Processor) Input Synchronous Linear / Interleaved Burst Order Input DC LBO ZZ Sleep Mode Input Asynchronous I/O0-I/O31, I/OP1-I/OP4 Data Input / Output I/O Synchronous VDD, VDDQ Core Power, I/O Power Supply N/A VSS Ground Supply N/A 5309 tbl 01 NOTE: 1. BW3 and BW4 are not applicable for the IDT71V67903. 6.42 2 Aug.11.21