CY7C25632KV18 CY7C25652KV18 72-Mbit QDR II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 72-Mbit QDR II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Phase-locked loop (PLL) for accurate data placement Features Configurations Separate independent read and write data ports Supports concurrent transactions With Read Cycle Latency of 2.5 cycles 550 MHz clock for high bandwidth CY7C25632KV18 4M 18 Four-word burst for reducing address bus frequency CY7C25652KV18 2M 36 Double data rate (DDR) interfaces on both read and write ports Functional Description (data transferred at 1100 MHz) at 550 MHz Available in 2.5 clock cycle latency The CY7C25632KV18 and CY7C25652KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II+ Two input clocks (K and K) for precise DDR timing architecture. Similar to QDR II architecture, QDR II+ architecture SRAM uses rising edges only consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data Echo clocks (CQ and CQ) simplify data capture in high-speed outputs to support read operations and the write port has systems dedicated data inputs to support write operations. QDR II+ Data valid pin (QVLD) to indicate valid data on the output architecture has separate data inputs and data outputs to completely eliminate the need to turn-around the data bus that On-die termination (ODT) feature exists with common I/O devices. Each port is accessed through Supported for D , BWS , and K/K inputs x:0 x:0 a common address bus. Addresses for read and write addresses are latched on alternate rising edges of the input (K) clock. Single multiplexed address input bus latches address inputs Accesses to the QDR II+ read and write ports are completely for read and write ports independent of one another. To maximize data throughput, both Separate port selects for depth expansion read and write ports are equipped with DDR interfaces. Each address location is associated with four 18-bit words Synchronous internally self-timed writes (CY7C25632KV18), or 36-bit words (CY7C25652KV18) that QDR II+ operates with 2.5 cycle read latency when DOFF is burst sequentially into or out of the device. Because data is asserted HIGH transferred into and out of the device on every rising edge of both input clocks (K and K), memory bandwidth is maximized while Operates similar to QDR I device with 1 cycle read latency when simplifying system design by eliminating bus turn-arounds. DOFF is asserted LOW These devices have an On-Die Termination feature supported Available in 18, and 36 configurations for D , BWS , and K/K inputs, which helps eliminate x:0 x:0 external termination resistors, reduce cost, reduce board area, Full data coherency, providing most current data and simplify board routing. 1 Core V = 1.8 V 0.1 V I/O V = 1.4 V to V DD DDQ DD Depth expansion is accomplished with port selects, which Supports both 1.5 V and 1.8 V I/O supply enables each port to operate independently. HSTL inputs and variable drive HSTL output buffers All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output Available in 165-ball FBGA package (13 15 1.4 mm) registers controlled by the K or K input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry. Offered in both Pb-free and non Pb-free packages For a complete list of related documentation, click here. JTAG 1149.1 compatible test access port Selection Guide Description 550 MHz 500 MHz 450 MHz 400 MHz Unit Maximum Operating Frequency 550 500 450 400 MHz Maximum Operating Current 18 920 850 780 710 mA 36 1310 1210 1100 1000 Note 1. The Cypress QDR II+ devices surpass the QDR consortium specification and can support V = 1.4 V to V . DDQ DD Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-66482 Rev. *I Revised November 28, 20171M x 18 Array 512K x 36 Array 1M x 18 Array 512K x 36 Array 1M x 18 Array 512K x 36 Array 1M x 18 Array 512K x 36 Array CY7C25632KV18 CY7C25652KV18 Logic Block Diagram CY7C25632KV18 18 D 17:0 Write Write Write Write 20 Address A Reg Reg Reg Reg (19:0) Register 20 Address A (19:0) Register K RPS Control CLK K Logic Gen. DOFF Read Data Reg. CQ 72 V 36 REF 18 CQ Reg. Reg. Control WPS 18 Logic 18 18 36 BWS Q Reg. 1:0 17:0 18 QVLD Logic Block Diagram CY7C25652KV18 36 D 35:0 Write Write Write Write 19 Address A Reg Reg Reg Reg (18:0) Register 19 Address A (18:0) Register RPS K Control CLK K Logic Gen. DOFF Read Data Reg. CQ 144 V 72 REF CQ 36 Reg. Reg. Control WPS 36 Logic 36 72 36 Q BWS Reg. 3:0 35:0 36 QVLD Document Number: 001-66482 Rev. *I Page 2 of 32 Write Add. Decode Write Add. Decode Read Add. Decode Read Add. Decode