256K X 36, 512K X 18 71V67603 3.3V Synchronous SRAMs 71V67803 3.3V I/O, Burst Counter Pipelined Outputs, Single Cycle Deselect Features 256K x 36, 512K x 18 memory configurations LBO input selects interleaved or linear burst mode Supports high system speed: 3.3V core power supply 166MHz 3.5ns clock access time Power down controlled by ZZ input 150MHz 3.8ns clock access time 3.3V I/O supply (VDDQ) 133MHz 4.2ns clock access time Packaged in a JEDEC Standard 100-pin thin plastic quad Self-timed write cycle with global write control (GW), byte flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch write enable (BWE), and byte writes (BWx) ball grid array (fBGA). Functional Block Diagram LBO ADV INTERNAL Burst CEN ADDRESS Sequence 256K x 36/ CLK 2 Burst 18/19 Binary 512K x 18- Logic Counter ADSC A0* BIT Q0 CLR MEMORY A1* Q1 ADSP ARRAY 2 CLK EN A0,A1 A2A18 A0A17/18 ADDRESS 36/18 REGISTER 36/18 18/19 GW Byte 1 BWE Write Register Byte 1 Write Driver BW1 9 Byte 2 Byte 2 Write Register Write Driver BW2 9 Byte 3 Write Register Byte 3 Write Driver BW3 9 Byte 4 Byte 4 Write Register Write Driver BW4 9 OUTPUT REGISTER CE Q D CS0 Enable DATA INPUT CS1 Register REGISTER CLK EN ZZ Powerdown DQ Enable Delay Register OE OUTPUT BUFFER OE , 36/18 I/O0I/O31 I/OP1I/OP4 5301 drw 01 1 Sep.13.2171V67603, 71V67803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Pipelined Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges Description access sequence. The first cycle of output data will be pipelined for one The IDT71V67603/7803 are high-speed SRAMs organized as cycle before it is available on the next rising clock edge. If burst mode 256K x 36/512K x 18. The IDT71V67603/7803 SRAMs contain write, operation is selected (ADV=LOW), the subsequent three cycles of output data, address and control registers. Internal logic allows the SRAM to data will be available to the user on the next three rising clock edges. The generate a self-timed write based upon a decision which can be left until order of these three addresses are defined by the internal burst counter the end of the write cycle. and the LBO input pin. The burst mode feature offers the highest level of performance to the The IDT71V67603/7803 SRAMs utilize a high-performance CMOS pro- system designer, as the IDT71V67603/7803 can provide four cycles of cess and are packaged in a JEDEC standard 14mm x 20mm 100-pin thin plastic data for a single address presented to the SRAM. An internal burst address quad flatpack (TQFP), a 119 ball grid array (BGA) and a 165 fine pitch ball counter accepts the first cycle address from the processor, initiating the grid array (fBGA). Pin Description Summary A0-A18 Address Inputs Input Synchronous Chip Enable Input Synchronous CE CS0, CS1 Chip Selects Input Synchronous Output Enable Input Asynchronous OE Global Write Enable Input Synchronous GW Byte Write Enable Input Synchronous BWE (1) Individual Byte Write Selects Input Synchronous BW1, BW2, BW3, BW4 CLK Clock Input N/A Burst Address Advance Input Synchronous ADV ADSC Address Status (Cache Controller) Input Synchronous Address Status (Processor) Input Synchronous ADSP Linear / Interleaved Burst Order Input DC LBO ZZ Sleep Mode Input Asynchronous I/O0-I/O31, I/OP1-I/OP4 Data Input / Output I/O Synchronous VDD, VDDQ Core Power, I/O Power Supply N/A VSS Ground Supply N/A 5310 tbl 01 NOTE: 1. BW3 and BW4 are not applicable for the IDT71V67803. 6.422 Sep.13.21