CY7C1460KV33 CY7C1460KVE33 CY7C1462KVE33 36-Mbit (1M 36/2M 18) Pipelined SRAM with NoBL Architecture (With ECC) 36-Mbit (1M 36/2M 18) Pipelined SRAM with NoBL Architecture (With ECC) Features Functional Description Pin-compatible and functionally equivalent to Zero Bus The CY7C1460KV33/CY7C1460KVE33/CY7C1462KVE33 are Turnaround (ZBT) 3.3 V, 1M 36, and 2M 18 synchronous pipelined burst SRAMs with No Bus Latency (NoBL) logic, respectively. They are Supports 250-MHz bus operations with zero wait states designed to support unlimited true back-to-back read/write Available speed grades are 250, 200, and 167 MHz operations with no wait states. The Internally self-timed output buffer control to eliminate the need CY7C1460KV33/CY7C1460KVE33/CY7C1462KVE33 devices to use asynchronous OE are equipped with the advanced (NoBL) logic required to enable consecutive read/write operations with data being transferred on Fully-registered (inputs and outputs) for pipelined operation every clock cycle. Byte write capability This feature dramatically improves the throughput of data in 3.3-V power supply systems that require frequent write and read transitions. The CY7C1460KV33/CY7C1460KVE33/CY7C1462KVE33 devices 3.3-V/2.5-V I/O power supply are pin-compatible and functionally equivalent to ZBT devices. Fast clock-to-output time All synchronous inputs pass through input registers controlled by 2.5 ns (for 250-MHz device) the rising edge of the clock. All data outputs pass through output Clock enable (CEN) pin to suspend operation registers controlled by the rising edge of the clock. The clock input is qualified by the clock enable (CEN) signal, which when Synchronous self-timed writes deasserted suspends operation and extends the previous clock CY7C1460KV33, CY7C1460KVE33, CY7C1462KVE33 cycle. available in JEDEC-standard Pb-free 100-pin TQFP, Pb-free Write operations are controlled by the byte write selects and non Pb-free 165-ball FBGA packages (BW BW for CY7C1460KV33/CY7C1460KVE33 and a d IEEE 1149.1 JTAG-compatible boundary scan BW BW for CY7C1462KVE33) and a write enable (WE) input. a b All writes are conducted with on-chip synchronous self-timed Burst capabilitylinear or interleaved burst order write circuitry. ZZ sleep mode option Three synchronous chip enables (CE , CE , and CE ) and an 1 2 3 On-chip Error Correction Code (ECC) to reduce Soft Error Rate asynchronous output enable (OE) enable easy bank selection (SER) and output tristate control. To avoid bus contention, the output drivers are synchronously tristated during the data portion of a write sequence. Selection Guide Description 250 MHz 200 MHz 167 MHz Unit Maximum access time 2.5 3.2 3.4 ns Maximum operating current 18 220 190 170 mA 36 240 210 190 Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-66680 Rev. *L Revised February 8, 2018 CY7C1460KV33 CY7C1460KVE33 CY7C1462KVE33 Logic Block Diagram CY7C1460KV33 ADDRESS A0, A1, A REGISTER 0 A1 A1 D1 Q1 A0 BURST A0 D0 Q0 MODE LOGIC ADV/LD CLK C C CEN WRITE ADDRESS WRITE ADDRESS REGISTER 1 REGISTER 2 O O S U D U E T T A P N P U T U T S ADV/LD A T E WRITE REGISTRY R MEMORY AND DATA COHERENCY WRITE E S B DQ s BW a ARRAY CONTROL LOGIC G U DRIVERS T DQ Pa BW b A I F BW c E DQ Pb M S F BW d T E DQ Pc E P E R R DQ Pd S WE R S I S E E N G INPUT INPUT E E REGISTER 1 REGISTER 0 OE READ LOGIC CE1 CE2 CE3 SLEEP ZZ CONTROL Logic Block Diagram CY7C1460KVE33 ADDRESS A0, A1, A REGISTER 0 A1 A1 D1 Q1 A0 A0 BURST D0 Q0 MODE LOGIC ADV/LD CLK C C CEN WRITE ADDRESS WRITE ADDRESS REGISTER 1 REGISTER 2 O O S U D E U E T T A C P N P U T C U S T ADV/LD A T E WRITE REGISTRY D R MEMORY AND DATA COHERENCY E S E B DQs BWA WRITE ARRAY CONTROL LOGIC G U DRIVERS T C DQPA BWB A I F E O BWC M DQPB S F E D BWD T DQPC P E E R E R DQPD WE S R S I R S E E N G ECC INPUT INPUT ENCODER REGISTER 1 E REGISTER 0 E OE READ LOGIC CE1 CE2 CE3 SLEEP ZZ CONTROL Document Number: 001-66680 Rev. *L Page 2 of 31