HIGH-SPEED 7006S/L 16K x 8 DUAL-PORT STATIC RAM M/S = H for BUSY output flag on Master, Features M/S = L for BUSY input on Slave True Dual-Ported memory cells which allow simultaneous Busy and Interrupt Flags reads of the same memory location On-chip port arbitration logic High-speed access Full on-chip hardware support of semaphore signaling Commercial: 15/17/20/25/35/55ns (max.) between ports Industrial: 20ns (max.) Fully asynchronous operation from either port Military: 20/25/35/55/70ns (max.) Devices are capable of withstanding greater than 2001V Low-power operation electrostatic discharge IDT7006S Battery backup operation2V data retention Active: 750mW (typ.) TTL-compatible, single 5V (10%) power supply Standby: 5mW (typ.) Available in 68-pin PGA, quad flatpack, PLCC, and a 64-pin IDT7006L TQFP Active: 700mW (typ.) Industrial temperature range (40C to +85C) is available Standby: 1mW (typ.) for selected speeds IDT7006 easily expands data bus width to 16 bits or more Green parts available, see ordering information using the Master/Slave select when cascading more than one device Functional Block Diagram OER OEL CEL CER R/WL R/WR I/O0L-I/O7L I/O0R-I/O7R I/O I/O Control Control (1,2) (1,2) BUSYL BUSYR A13L A13R Address MEMORY Address Decoder ARRAY Decoder A0L A0R 14 14 ARBITRATION CEL CER INTERRUPT OER OEL SEMAPHORE LOGIC R/WR R/WL SEML SEMR M/S (2) (2) INTL INTR 2739 drw 01 NOTES: 1. (MASTER): BUSY is output (SLAVE): BUSY is input. 2. BUSY outputs and INT outputs are non-tri-stated push-pull. 1 Jan.30.207006S/L High-Speed 16K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges Description The IDT7006 is a high-speed 16K x 8 Dual-Port Static RAM. The a very low standby power mode. IDT7006 is designed to be used as a stand-alone 128K-bit Dual-Port RAM Fabricated using CMOS high-performance technology, these de- or as a combination MASTER/SLAVE Dual-Port RAM for 16-bit-or-more vices typically operate on only 750mW of power. Low-power (L) versions word systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach offer battery backup data retention capability with typical power consump- in 16-bit or wider memory system applications results in full-speed, error- tion of 500W from a 2V battery. free operation without the need for additional discrete logic. The IDT7006 is packaged in a ceramic 68-pin PGA, an 68-pin quad This device provides two independent ports with separate control, flatpack, a PLCC, and a 64-pin thin quad flatpack, TQFP. Military grade address, and I/O pins that permit independent, asynchronous access for product is manufactured in compliance with the latest revision of MIL-PRF- reads or writes to any location in memory. An automatic power down 38535 QML, Class B, making it ideally suited to military temperature feature controlled by CE permits the on-chip circuitry of each port to enter applications demanding the highest level of performance and reliability. (1,2,3) Pin Configurations 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 I/O7R 27 9 I/O1L N/C 28 8 I/O0L OER 29 7 N/C R/WR 30 6 OEL 31 5 SEMR R/WL 32 4 CER SEML 33 3 N/C CEL 7006 34 A13R 2 N/C (4) PLG68 35 GND 1 A13L A12R 36 68 VCC 68-Pin PLCC 37 A11R 67 A12L Top View A10R 38 66 A11L 65 A9R 39 A10L 40 A8R 64 A9L A7R 41 63 A8L A6R 42 62 A7L 43 A5R 61 A6L 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 2739 drw 02 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 61 A6L 43 A5R 62 A7L 42 A6R 63 A8L 41 A7R 64 A9L 40 A8R A10L 65 39 A9R 66 A11L 38 A10R 67 A12L 37 A11R 68 VCC 36 A12R 7006 A13L 1 (4) 35 GND FP68 2 N/C 34 A13R 3 CEL 68 Pin Flatpack 33 N/C SEML 4 Top View 32 CER R/WL 5 31 SEMR 6 OEL 30 R/WR 7 N/C 29 OER NOTES: 8 I/O0L 28 N/C 1. All VCC pins must be connected to power supply. 9 I/O1L 27 I/O7R 2. All GND pins must be connected to ground supply. 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 3. PLG68 package body is approximately .95 in x .95 in. x .17 in. 2739 drw 02a FP68 package body is approximately .97 in x .97 in x .08 in. 4. This package code is used to reference the package diagram. 2 Jan.30.20 I/O6R A4R I/O5R A3R I/O4R A2R A1R I/O3R A0R VCC INTR I/O2R BUSYR I/O1R M/S I/O0R GND GND BUSYL VCC INTL I/O7L A0L I/O6L A1L GND A2L I/O5L A3L I/O4L A4L I/O3L A5L I/O2L I/O2L A5L I/O3L A4L I/O4L A3L I/O5L A2L GND A1L I/O6L A0L I/O7L INTL VCC BUSYL GND GND I/O0R M/S I/O1R BUSYR I/O2R INTR VCC A0R I/O3R A1R I/O4R A2R I/O5R A3R I/O6R A4R