HIGH-SPEED 7025S/L 8K x 16 DUAL-PORT STATIC RAM IDT7025 easily expands data bus width to 32 bits or more Features using the Master/Slave select when cascading more than True Dual-Ported memory cells which allow simultaneous one device reads of the same memory location M/S = H for BUSY output flag on Master High-speed access M/S = L for BUSY input on Slave Commercial: 15/17/20/25/35/55ns (max.) Interrupt Flag Industrial: 20ns (max.) On-chip port arbitration logic Military: 20/25/35/55/70ns (max.) Full on-chip hardware support of semaphore signaling Low-power operation between ports IDT7025S Fully asynchronous operation from either port Active: 750mW (typ.) Battery backup operation2V data retention Standby: 5mW (typ.) TTL-compatible, single 5V (10%) power supply IDT7025L Available in 84-pin PGA, Flatpack, PLCC, and 100-pin Thin Active: 750mW (typ.) Quad Flatpack Standby: 1mW (typ.) Industrial temperature range (40C to +85C) is available Separate upper-byte and lower-byte control for multiplexed for selected speeds bus compatibility Green parts available, see ordering information Functional Block Diagram R/WL R/WR UBR UBL LBL LBR CEL CER OEL OER I/O8L-I/O15L I/O8R-I/O15R I/O I/O Control Control I/O0R-I/O7R I/O0L-I/O7L (1,2) (1,2) BUSYR BUSYL A12R A12L Address MEMORY Address Decoder ARRAY Decoder A0L A0R 13 13 ARBITRATION CEL INTERRUPT CER SEMAPHORE OEL OER LOGIC R/WL R/WR SEML SEMR (2) (2) INTR M/S INTL 2683 drw 01 NOTES: 1. (MASTER): BUSY is output (SLAVE): BUSY is input. 2. BUSY outputs and INT outputs are non-tri-stated push-pull. OCTOBER 2019 1 DSC 2683/137025S/L High-Speed 8K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges Description feature controlled by Chip Enable (CE) permits the on-chip circuitry of each port to enter a very low standby power mode. The IDT7025 is a high-speed 8K x 16 Dual-Port Static RAM. The Fabricated using CMOS high-performance technology, these de- IDT7025 is designed to be used as a stand-alone 128K-bit Dual-Port RAM vices typically operate on only 750mW of power. Low-power (L) versions or as a combination MASTER/SLAVE Dual-Port RAM for 32-bit or more offer battery backup data retention capability with typical power consump- word systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach tion of 500W from a 2V battery. in 32-bit or wider memory system applications results in full-speed, error- The IDT7025 is packaged in a ceramic 84-pin PGA, an 84-pin free operation without the need for additional discrete logic. Flatpack, PLCC, and a 100-pin TQFP. Military grade product is manu- This device provides two independent ports with separate control, factured in compliance with the latest revision of MIL-PRF-38535 QML, address, and I/O pins that permit independent, asynchronous access for making it ideally suited to military temperature applications demanding the reads or writes to any location in memory. An automatic power down highest level of performance and reliability. (1,2,3) Pin Configurations INDEX 1110 9 8 7 6 5 4 3 2 1 8483 82 81 80 79 78 77 76 75 A7L I/O8L 12 74 A6L I/O9L 13 73 A5L I/O10L 72 14 A4L I/O11L 71 15 A3L I/O12L 70 16 A2L I/O13L 69 17 A1L GND 68 18 A0L I/O14L 7025 67 19 PLG84(4) INTL I/O15L 66 20 (4) FP84 VCC 65 BUSYL 21 GND 84-Pin PLCC/Flatpack 64 GND 22 (5) Top View I/O0R 63 23 M/S I/O1R 62 24 BUSYR I/O2R 25 61 INTR VCC 26 60 A0R I/O3R 27 59 A1R I/O4R 28 58 A2R I/O5R 29 57 A3R I/O6R 30 56 A4R I/O7R 31 55 A5R A6R I/O8R 32 54 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 . 2683 drw 02 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 A6L 76 50 A5R 49 A7L 77 A6R 48 A8L 78 A7R 79 47 A9L A8R 80 46 A10L A9R 45 A11L 81 A10R 44 A12L 82 A11R LBL 83 43 A12R UBL 42 84 LBR 41 CEL 85 UBR SEML 86 40 CER 39 R/WL 87 7025 SEMR (4) PNG100 38 VCC 88 GND 37 OEL 89 R/WR 100-Pin TQFP 36 I/O0L 90 OER Top View 91 35 I/O15R I/O1L 34 GND GND 92 33 I/O14R I/O2L 93 NOTES: I/O3L 94 32 I/O13R 1. All VCC pins must be connected to power supply. I/O4L 95 31 I/O12R 96 30 I/O5L I/O11R 2. All GND pins must be connected to ground supply. 97 I/O6L 29 I/O10R 3. PLG84 package body is approximately 1.15 in x 1.15 in x .17 in. I/O7L 98 28 I/O9R FP84 package body is approximately 1.17 in x 1.17 in x .11 in. 99 27 I/O8R I/O8L PNG100 package body is approximately 14mm x 14mm x 1.4mm. I/O9L 100 26 I/O7R 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 4. This package code is used to reference the package diagram. 2683 drw 03 5. This text does not indicate orientation of the actual part-marking. 6.422 I/O9R I/O7L I/O10R I/O6L I/O11R I/O5L I/O12R I/O4L I/O13R I/O3L I/O14R I/O2L GND GND I/O15R I/O1L OER I/O0L R/WR OEL GND VCC SEMR R/WL CER SEML UBR CEL LBR UBL A12R LBL A11R A12L A10R A11L A9R A10L A8R A9L A7R A8L N/C N/C N/C N/C N/C N/C N/C N/C I/O10L A5L I/O11L A4L I/O12L A3L I/O13L A2L GND A1L I/O14L A0L I/O15L INTL VCC BUSYL GND GND I/O0R M/S I/O1R BUSYR I/O2R INTR VCC A0R I/O3R A1R I/O4R A2R I/O5R A3R I/O6R A4R N/C N/C N/C N/C N/C N/C N/C N/C