CY7C1041G CY7C1041GE 4-Mbit (256K words 16-bit) Static RAM with Error-Correcting Code (ECC) 4-Mbit (256K words 16-bit) Static RAM with Error-Correcting Code (ECC) Data writes are performed by asserting the Chip Enable (CE) and Features Write Enable (WE) inputs LOW, while providing the data on I/O 0 High speed through I/O and address on A through A pins. The Byte High 15 0 17 t = 10 ns/15 ns Enable (BHE) and Byte Low Enable (BLE) inputs control write AA 1, 2 operations to the upper and lower bytes of the specified memory Embedded ECC for single-bit error correction location. BHE controls I/O through I/O and BLE controls I/O 8 15 0 Low active and standby currents through I/O . 7 Active current: I = 38 mA typical CC Data reads are performed by asserting the Chip Enable (CE) and Standby current: I = 6 mA typical SB2 Output Enable (OE) inputs LOW and providing the required Operating voltage range: 1.65 V to 2.2 V, 2.2 V to 3.6 V, and address on the address lines. Read data is accessible on the I/O 4.5 V to 5.5 V lines (I/O through I/O ). Byte accesses can be performed by 0 15 asserting the required byte enable signal (BHE or BLE) to read 1.0-V data retention either the upper byte or the lower byte of data from the specified address location. TTL-compatible inputs and outputs All I/Os (I/O through I/O ) are placed in a high-impedance state 0 15 Error indication (ERR) pin to indicate 1-bit error detection and during the following events: correction The device is deselected (CE HIGH) Pb-free 44-pin SOJ, 44-pin TSOP II, and 48-ball VFBGA packages The control signals (OE, BLE, BHE) are de-asserted On the CY7C1041GE devices, the detection and correction of a Functional Description single-bit error in the accessed location is indicated by the 1 CY7C1041G and CY7C1041GE are high-performance CMOS assertion of the ERR output (ERR = HIGH) . See the Truth Table on page 14 for a complete description of read and write fast static RAM devices with embedded ECC. Both devices are modes. offered in single chip-enable option and in multiple pin configurations. The CY7C1041GE device includes an ERR pin The logic block diagram is on page 2. that signals an error-detection and correction event during a read cycle. Product Portfolio Power Dissipation Speed Operating I , (mA) Features and Options (see Pin V Range (ns) CC Standby, I 3 CC SB2 Product Range Configurations on page 4) (V) (mA) f = f max 10/15 4 4 Typ Max Typ Max CY7C1041G(E)18 Single Chip Enable Industrial 1.65 V2.2 V 15 40 6 8 CY7C1041G(E)30 2.2 V3.6 V 10 38 45 Optional ERR pins CY7C1041G(E) 4.5 V5.5 V 10 38 45 Notes 1. This device does not support automatic write-back on error detection. 2. SER FIT Rate <0.1 FIT/Mb. Refer AN88889 for details. 3. The ERR pin is available only for devices which have ERR option E in the ordering code. Refer Ordering Information on page 15 for details. 4. Typical values are included only for reference and are not guaranteed or tested. Typical values are measured at V = 1.8 V (for a V range of 1.65 V2.2 V), CC CC V =3V (for a V range of 2.2 V3.6 V), and V = 5 V (for a V range of 4.5 V5.5 V), T = 25 C. CC CC CC CC A Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-91368 Rev. *N Revised July 13, 2018CY7C1041G CY7C1041GE Logic Block Diagram CY7C1041G ECCENCODER INPUTBUFFER A0 A1 A2 A3 I/O I/O 0 7 MEMORY A4 ARRAY A5 I/O I/O 8 15 A6 A7 A8 A9 COLUMNDECODER BHE WE CE OE BLE Logic Block Diagram CY7C1041GE ECCENCODER INPUTBUFFER A0 A1 ERR A2 A3 I/O I/O 0 7 MEMORY A4 ARRAY I/O I/O A5 8 15 A6 A7 A8 A9 COLUMNDECODER BHE WE CE OE BLE Document Number: 001-91368 Rev. *N Page 2 of 21 ROWDECODER ROWDECODER A10 A11 A12 A10 A13 A11 A14 A12 A15 A13 A16 A14 A17 A15 A16 A17 SENSE AMPLIFIERS SENSE AMPLIFIERS ECCDECODER ECCDECODER