CY7C1360C, CY7C1362C 9-Mbit (256 K 36/512 K 18) Pipelined SRAM 9-Mbit (256 K 36/512 K 18) Pipelined SRAM Features Functional Description Supports bus operation up to 200 MHz The CY7C1360C/CY7C1362C SRAM integrates 256 K 36 and 512 K 18 SRAM cells with advanced synchronous peripheral Available speed grades: 200 MHz, and 166 MHz circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a Registered inputs and outputs for pipelined operation positive-edge-triggered clock input (CLK). The synchronous 3.3 V core power supply (V ) DD inputs include all addresses, all data inputs, address-pipelining chip enable (CE ), depth-expansion chip enables (CE and 1 2 2.5 V/3.3 V I/O operation (V ) DDQ 1 CE ), burst control inputs (ADSC, ADSP, ADV), write and 3 Fast clock-to-output times enables (BW , and BWE), and global write (GW). Asynchronous X inputs include the output enable (OE) and the ZZ pin. 3.0 ns (for 200 MHz device) Addresses and chip enables are registered at the rising edge of Provide high performance 3-1-1-1 access rate clock when either address strobe processor (ADSP) or address User selectable burst counter supporting Intel Pentium strobe controller (ADSC) are active. Subsequent burst interleaved or linear burst sequences addresses can be internally generated as controlled by the advance pin (ADV). Separate processor and controller address strobes Address, data inputs, and write controls are registered on-chip Synchronous self-timed writes to initiate a self-timed write cycle.This part supports byte write operations (see Pin Definitions on page 8 and Truth Table on Asynchronous output enable page 11 for further details). Write cycles can be one to two or four Single cycle chip deselect bytes wide as controlled by the byte write control inputs. GW when active LOW cause s all bytes to be written. Available in Pb-free 100-pin TQFP package, non Pb-free The CY7C1360C/CY7C1362C operate from a +3.3 V core power 119-ball BGA package, and 165-ball FBGA package supply while all outputs may operate with either a +2.5 or +3.3 V TQFP available with 3-chip enable and 2-chip enable supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible. IEEE 1149.1 JTAG-compatible boundary scan Selection Guide Description 200 MHz 166 MHz Unit Maximum access time 3.0 3.5 ns Maximum operating current 220 180 mA Maximum CMOS standby current 40 40 mA Note 1. CE is for A version of TQFP (3 Chip Enable option) and 165-ball FBGA package only. 119-ball BGA is offered only in 2 Chip Enable. 3 Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-05540 Rev. *N Revised September 25, 2012CY7C1360C, CY7C1362C Logic Block Diagram CY7C1360C A0, A1, A ADDRESS REGISTER 2 A 1:0 MODE ADV Q1 BURST CLK COUNTER AND CLR Q0 LOGIC ADSC ADSP DQD ,DQP D DQ D ,DQPD BYTE BYTE BW D WRITE REGISTER WRITE DRIVER DQC ,DQP C DQC ,DQP C BYTE BYTE BW C OUTPUT WRITE DRIVER OUTPUT WRITE REGISTER MEMORY DQs SENSE BUFFERS ARRAY REGISTERS AMPS DQP A DQB ,DQP B E DQB ,DQP B DQP B BYTE BYTE BW B DQP C WRITE DRIVER WRITE REGISTER DQP D DQA ,DQP A DQA ,DQP A BYTE BW A BYTE WRITE DRIVER WRITE REGISTER BWE INPUT GW REGISTERS ENABLE PIPELINED CE 1 REGISTER ENABLE CE 2 CE 3 OE SLEEP ZZ CONTROL Logic Block Diagram CY7C1362C ADDRESS A0, A1, A REGISTER A 1:0 2 MODE ADV Q1 BURST CLK COUNTER AND LOGIC CLR Q0 ADSC ADSP DQ B,DQP B DQ B,DQP B WRITE DRIVER WRITE REGISTER BW B OUTPUT DQs SENSE OUTPUT MEMORY BUFFERS DQP A AMPS REGISTERS ARRAY DQP B DQ A, DQP A E DQ A, DQP A WRITE DRIVER BW A WRITE REGISTER BWE INPUT GW REGISTERS ENABLE CE 1 PIPELINED REGISTER CE2 ENABLE CE3 OE SLEEP ZZ CONTROL Document Number: 38-05540 Rev. *N Page 2 of 37