HIGH-SPEED 3.3V 512K x 18 70V7339S SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE Features: 1.5ns setup to clock and 0.5ns hold on all control, data, and 512K x 18 Synchronous Bank-Switchable Dual-ported address inputs 200MHz SRAM Architecture Data input, address, byte enable and control registers 64 independent 8K x 18 banks Self-timed write allows fast cycle time 9 megabits of memory on chip Separate byte controls for multiplexed bus and bus Bank access controlled via bank address pins matching compatibility High-speed data access LVTTL- compatible, 3.3V (150mV) power supply Commercial: 3.4ns (200MHz)/3.6ns (166MHz)/ for core 4.2ns (133MHz) (max.) LVTTL compatible, selectable 3.3V (150mV) or 2.5V Industrial: 3.6ns (166MHz)/4.2ns (133MHz) (max.) (100mV) power supply for I/Os and control signals on Selectable Pipelined or Flow-Through output mode each port Counter enable and repeat features Industrial temperature range (-40C to +85C) is Dual chip enables allow for depth expansion without available at 166MHz and 133MHz additional logic Available in 208-pin fine pitch Ball Grid Array (fpBGA) and Full synchronous operation on both ports 256-pin Ball Grid Array (BGA) 5ns cycle time, 200MHz operation (14Gbps bandwidth) Supports JTAG features compliant with IEEE 1149.1 Fast 3.4ns clock to data out Green parts available, see ordering information Functional Block Diagram PL/FTL PL/FTR OPTL OPTR CLKL CLKR ADSL ADSR CNTENL CNTENR REPEATL REPEATR R/WL R/WR MUX CONTROL CONTROL CE0L CE0R LOGIC LOGIC CE1L CE1R 8Kx18 UBL UBR MEMORY LBL LBR ARRAY OEL OER (BANK 0) MUX MUX I/O I/O I/O0L-17L I/O0R-17R CONTROL CONTROL 8Kx18 MEMORY ARRAY (BANK 1) A12R A12L ADDRESS ADDRESS DECODE DECODE A0R A0L MUX BA5R BA5L BA4R BA4L BANK BA3R BA3L BANK BA2L DECODE BA2R DECODE BA1L MUX BA1R BA0R BA0L 8Kx18 MEMORY ARRAY (BANK 63) MUX NOTE: 1. The Bank-Switchable dual-port uses a true SRAM , core instead of the traditional dual-port SRAM core. 5628 drw 01 TMS TDI As a result, it has unique operating characteristics. TCK JTAG TDO Please refer to the functional description on page 18 TRST for details. OCTOBER 2019 1 DSC 5628/12 2019 Integrated Device Technology, Inc.70V7339S High-Speed 512K x 18 Synchronous Bank-Switchable Dual-Port Static RAM Industrial and Commercial Temperature Ranges Description: The IDT70V7339 is a high-speed 512Kx18 (9Mbit) synchronous register, the IDT70V7339 has been optimized for applications having Bank-Switchable Dual-Ported SRAM organized into 64 independent unidirectional or bidirectional data flow in bursts. An automatic power down 8Kx18 banks. The device has two independent ports with separate feature, controlled by CE0 and CE1, permits the on-chip circuitry of each control, address, and I/O pins for each port, allowing each port to access port to enter a very low standby power mode. The dual chip enables also any 8Kx18 memory block not already accessed by the other port. facilitate depth expansion. Accesses by the ports into specific banks are controlled via the bank The 70V7339 can support an operating voltage of either 3.3V or 2.5V address pins under the user s direct control. on one or both ports, controllable by the OPT pins. The power supply for Registers on control, data, and address inputs provide minimal setup the core of the device(VDD) remains at 3.3V. Please refer also to the and hold times. The timing latitude provided by this approach allows functional description on page 18. systems to be designed with very short cycle times. With an input data (1,2,3,4) Pin Configuration A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 IO9L NC VSS BA3L A12L A8L NC CLKL CNTENL A4L A0L VSS TDO NC VDD OPTL NC B1 B2 B3 B6 B7 B9 B11 B12 B13 B17 B4 B5 B8 B10 B14 B15 B16 NC VSS NC BA0L A9L CE0L ADSL A5L A1L NC TDI BA4L NC VSS VSS VDDQR I/O8L C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C16 C14 C15 C17 VDDQL I/O9R VDDQR PL/FTL BA5L BA1L A10L UBL CE1L VSS R/WL A6L A2L NC VDD I/O8R VSS D1 D2 D3 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D4 NC VSS I/O10L BA2L A11L A7L LBL VDD OEL REPEATL A3L VDD NC VDDQL I/O7L I/O7R NC E1 E2 E3 E4 E14 E15 E16 E17 I/O11L NC VDDQR I/O10R I/O6L VSS NC NC F1 F2 F3 F14 F15 F16 F17 F4 VDDQL I/O11R NC VSS I/O6R NC VDDQR VSS G1 G2 G3 G4 G14 G15 G16 G17 NC VSS I/O12L NC NC VDDQL I/O5L NC 70V7339 H3 H4 H1 H2 H14 H15 H16 H17 VDD NC VDDQR I/O12R (5) VSS I/O5R VDD NC BF208 (5) J1 J2 J3 J4 J14 J15 J16 J17 BFG208 VDDQL VDD VSS VSS VSS VDD VSS VDDQR K2 K4 K15 K16 K1 K3 K14 K17 208-Pin fpBGA VSS VSS VDDQL I/O4R I/O14R I/O13R I/O3R VSS (6) Top View L1 L2 L3 L4 L14 L15 L16 L17 NC I/O14L VDDQR I/O13L NC I/O3L VSS I/O4L M1 M2 M3 M4 M16 M17 M14 M15 VDDQL NC I/O15R VSS I/O2R VDDQR VSS NC N16 N17 N1 N2 N3 N4 N14 N15 NC I/O2L NC VSS NC I/O15L I/O1R VDDQL P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 I/O16R I/O16L VDDQR NC TRST BA3R A12R A8R NC VDD CLKR CNTENR A4R NC I/O1L VSS NC R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R16 R17 R15 VSS NC I/O17R TCK BA4R BA0R A9R NC CE0R VSS ADSR A5R A1R VSS I/O0R VDDQR VDDQL T1 T2 T3 T4 T5 T8 T9 T15 T16 T17 T6 T7 T10 T11 T12 T13 T14 NC I/O17L VDDQL TMS BA5R UBR CE1R NC VSS NC BA1R A10R VSS R/WR A6R A2R VSS U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 VSS NC PL/FTR NC BA2R A11R A7R LBR VDD OER REPEATR A3R A0R VDD OPTR NC I/O0L 5628 drw 02c NOTES: 1. All VDD pins must be connected to 3.3V power supply. 2. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VIH (3.3V), and 2.5V if OPT pin for that port is set to VIL (0V). 3. All VSS pins must be connected to ground supply. 4. Package body is approximately 15mm x 15mm x 1.4mm with 0.8mm ball pitch. 5. This package code is used to reference the package diagram. 6. This text does not indicate orientation of the actual part-marking. 6.42 2