CY7C1325G 4-Mbit (256 K 18) Flow-Through Sync SRAM 4-Mbit (256 K 18) Flow-Through Sync SRAM Features Functional Description 256 K 18 common I/O The CY7C1325G is a 256 K 18 synchronous cache RAM designed to interface with high speed microprocessors with 3.3 V core power supply (V ) DD minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133 MHz version). A 2 bit on-chip counter captures the 2.5 V or 3.3 V I/O power supply (V ) DDQ first address in a burst and increments the address automatically Fast clock-to-output times for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input 6.5 ns (133 MHz version) (CLK). The synchronous inputs include all addresses, all data Provide high performance 2-1-1-1 access rate inputs, address-pipelining chip enable (CE ), depth-expansion 1 chip enables (CE and CE ), burst control inputs (ADSC, ADSP, 2 3 User selectable burst counter supporting Intel Pentium and ADV), write enables (BW , and BWE), and global write A:B interleaved or linear burst sequences (GW). Asynchronous inputs include the output enable (OE) and the ZZ pin. Separate processor and controller address strobes The CY7C1325G allows either interleaved or linear burst Synchronous self timed write sequences, selected by the MODE input pin. A HIGH selects an Asynchronous output enable interleaved burst sequence, while a LOW selects a linear burst sequence. Burst accesses can be initiated with the processor Available in Pb-free 100-pin TQFP package address strobe (ADSP) or the cache controller address strobe (ADSC) inputs. ZZ sleep mode option Addresses and chip enables are registered at rising edge of clock when either address strobe processor (ADSP) or address strobe controller (ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the advance pin (ADV). The CY7C1325G operates from a +3.3 V core power supply while all outputs may operate with either a +2.5 or +3.3 V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible. Logic Block Diagram ADDRESS A 0,A1,A REGISTER A 1:0 MODE ADV Q1 BURST CLK COUNTER AND LOGIC CLR Q0 ADSC ADSP DQ B,DQP B DQ B,DQP B WRITE DRIVER WRITE REGISTER BW B MEMORY OUTPUT DQs SENSE ARRAY BUFFERS AMPS DQP A DQ A,DQP A DQP B DQ A,DQP A WRITE DRIVER BW A WRITE REGISTER BWE INPUT GW REGISTERS ENABLE CE 1 REGISTER CE 2 CE 3 OE SLEEP ZZ CONTROL Errata: For information on silicon errata, seeErrat on page 21. Details include trigger conditions, devices affected, and proposed workaround. Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-05518 Rev. *N Revised October 7, 2013CY7C1325G Contents Selection Guide ................................................................3 Switching Characteristics .............................................. 13 Pin Configurations ...........................................................3 Timing Diagrams ............................................................ 14 Pin Definitions ..................................................................4 Ordering Information ...................................................... 18 Functional Overview ........................................................6 Ordering Code Definitions ......................................... 18 Single Read Accesses ................................................6 Package Diagrams .......................................................... 19 Single Write Accesses Initiated by ADSP ...................6 Acronyms ........................................................................20 Single Write Accesses Initiated by ADSC ...................6 Document Conventions ................................................. 20 Burst Sequences .........................................................6 Units of Measure ....................................................... 20 Sleep Mode .................................................................6 Errata ...............................................................................21 Interleaved Burst Address Table .................................7 Part Numbers Affected .............................................. 21 Linear Burst Address Table .........................................7 Product Status ........................................................... 21 ZZ Mode Electrical Characteristics ..............................7 Ram9 Sync ZZ Pin Issues Errata Summary .............. 21 Truth Table ........................................................................8 Document History Page ................................................. 22 Truth Table for Read/Write ..............................................9 Sales, Solutions, and Legal Information ...................... 24 Maximum Ratings ...........................................................10 Worldwide Sales and Design Support ....................... 24 Operating Range .............................................................10 Products ....................................................................24 Neutron Soft Error Immunity .........................................10 PSoC Solutions ...................................................... 24 Electrical Characteristics ...............................................10 Cypress Developer Community ................................. 24 Capacitance ....................................................................11 Technical Support ..................................................... 24 Thermal Resistance ........................................................11 AC Test Loads and Waveforms .....................................12 Document Number: 38-05518 Rev. *N Page 2 of 24