CY7C1361C/CY7C1363C 9-Mbit (256 K 36/512 K 18) Flow-Through SRAM 9-Mbit (256 K 36/512 K 18) Flow-through SRAM Features Functional Description Supports 100 MHz, 133 MHz bus operations The CY7C1361C/CY7C1363C is a 3.3 V, 256 K 36/512 K 18 synchronous flow-through SRAMs, respectively designed to Supports 100 MHz bus operations (Automotive) interface with high speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133 MHz 256 K 36/512 K 18 common I/O version). A 2-bit on-chip counter captures the first address in a 3.3 V 5% and +10% core power supply (V ) DD burst and increments the address automatically for the rest of the burst access. All synchronous inputs are gated by registers 2.5 V or 3.3 V I/O power supply (V ) DDQ controlled by a positive-edge-triggered clock input (CLK). The Fast clock-to-output times synchronous inputs include all addresses, all data inputs, address-pipelining chip enable (CE ), depth-expansion chip 6.5 ns (133-MHz version) 1 1 enables (CE and CE ), burst control inputs (ADSC, ADSP, 2 3 Provide high performance 2-1-1-1 access rate and ADV), write enables (BW , and BWE), and global write x (GW). Asynchronous inputs include the output enable (OE) and User-selectable burst counter supporting Intel Pentium the ZZ pin. interleaved or linear burst sequences The CY7C1361C/CY7C1363C enables either interleaved or Separate processor and controller address strobes linear burst sequences, selected by the MODE input pin. A HIGH Synchronous self-timed write selects an interleaved burst sequence, while a LOW selects a linear burst sequence. Burst accesses can be initiated with the Asynchronous output enable processor address strobe (ADSP) or the cache controller address strobe (ADSC) inputs. Address advancement is Available in Pb-free 100-pin TQFP package and non Pb-free controlled by the address advancement (ADV) input. 119-ball BGA package Addresses and chip enables are registered at rising edge of TQFP available with 3-chip enable and 2-chip enable clock when either address strobe processor (ADSP) or address strobe controller (ADSC) are active. Subsequent burst IEEE 1149.1 JTAG-compatible boundary scan addresses can be internally generated as controlled by the ZZ sleep mode option advance pin (ADV). The CY7C1361C/CY7C1363C operates from a +3.3 V core power supply while all outputs may operate with either a +2.5 or +3.3 V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible. Selection Guide Description 133 MHz 100 MHz Unit Maximum access time 6.5 8.5 ns Maximum operating current 250 180 mA Maximum CMOS standby current Commercial/Industrial 40 40 mA Automotive 60 mA Note 1. CE is for A version of 100-pin TQFP (3 Chip Enable Option). 119-ball BGA is offered only in 2 Chip Enable. 3 Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-05541 Rev. *N Revised September 3, 2013CY7C1361C/CY7C1363C Logic Block Diagram CY7C1361C ADDRESS A0, A1, A REGISTER A 1:0 MODE ADV Q1 BURST CLK COUNTER AND LOGIC Q0 CLR ADSC ADSP DQ D, DQP D DQ D, DQP D BYTE BW D BYTEBYTE WRITE REGISTER WRITE REGISTERWRITE REGISTER DQ C, DQP C DQ C, DQP C BW C BYTE BYTE WRITE REGISTER WRITE REGISTER OUTPUT DQ s MEMORY SENSE BUFFERS ARRAY DQP A DQ B, DQP B AMPS DQ B, DQP B DQP B BYTE BW B DQP C BYTE WRITE REGISTER DQP D WRITE REGISTER DQ A, DQP A DQ A, DQPA BYTE BW A BYTE WRITE REGISTER BWE WRITE REGISTER INPUT GW REGISTERS ENABLE CE1 REGISTER CE2 CE3 OE SLEEP ZZ CONTROL Logic Block Diagram CY7C1363C ADDRESS A 0,A1,A REGISTER A 1:0 MODE ADV Q1 BURST CLK COUNTER AND LOGIC CLR Q0 ADSC ADSP DQ B,DQP B DQ B,DQP B WRITE DRIVER WRITE REGISTER BW B MEMORY OUTPUT DQs SENSE ARRAY BUFFERS AMPS DQP A DQ A,DQP A DQP B DQ A,DQP A WRITE DRIVER BW A WRITE REGISTER BWE INPUT GW REGISTERS ENABLE CE 1 REGISTER CE 2 CE 3 OE SLEEP ZZ CONTROL Document Number: 38-05541 Rev. *N Page 2 of 34