HIGH-SPEED 7024S/L 4K x 16 DUAL-PORT STATIC RAM IDT7024 easily expands data bus width to 32 bits or more Features using the Master/Slave select when cascading more than True Dual-Ported memory cells which allow simultaneous one device reads of the same memory location M/S = H for BUSY output flag on Master High-speed access M/S = L for BUSY input on Slave Commercial: 15/17/20/25/35/55ns (max.) Interrupt Flag Industrial: 20ns (max.) On-chip port arbitration logic Military: 20/25/35/55/70ns (max.) Full on-chip hardware support of semaphore signaling Low-power operation between ports IDT7024S Fully asynchronous operation from either port Active: 750mW (typ.) Battery backup operation2V data retention Standby: 5mW (typ.) TTL-compatible, single 5V (10%) power supply IDT7024L Available in 84-pin PGA, Flatpack, PLCC, and 100-pin Thin Active: 750mW (typ.) Quad Flatpack Standby: 1mW (typ.) Industrial temperature range (40C to +85C) is available Separate upper-byte and lower-byte control for multiplexed for selected speeds bus compatibility Green parts available, see ordering information Functional Block Diagram R/WL R/WR UBR UBL LBL LBR CER CEL OER OEL I/O8L-I/O15L I/O8R-I/O15R I/O I/O Control Control I/O0L-I/O7L I/O0R-I/O7R (1,2) (1,2) BUSYL BUSYR A11R A11L Address MEMORY Address Decoder ARRAY Decoder A0L A0R 12 12 ARBITRATION CER CEL INTERRUPT OER OEL SEMAPHORE LOGIC R/WR R/WL SEMR SEML (2) (2) M/S INTR INTL 2740 drw 01 NOTES: 1. (MASTER): BUSY is output (SLAVE): BUSY is input. 2. BUSY outputs and INT outputs are non-tri-stated push-pull. 1 Feb.20.207024S/L High-Speed 4K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges Description The IDT7024 is a high-speed 4Kx 16 Dual-Port Static RAM. The port to enter a very low standby power mode. Fabricated using CMOS high-performance technology, these devices IDT7024 is designed to be used as a stand-alone 64K-bit Dual-Port RAM typically operate on only 750mW of power. Low-power (L) versions offer or as a combination MASTER/SLAVE Dual-Port RAM for 32-bit or more word systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach battery backup data retention capability with typical power consumption of in 32-bit or wider memory system applications results in full-speed, error- 500W from a 2V battery. free operation without the need for additional discrete logic. The IDT7024 is packaged in a ceramic 84-pin PGA, an 84-pin Flatpack and PLCC, and a 100-pin TQFP. Military grade product is manufactured This device provides two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for in compliance with the latest revision of MIL-PRF-38535 QML, making it reads or writes to any location in memory. An automatic power down ideally suited to military temperature applications demanding the highest feature controlled by chip enable (CE) permits the on-chip circuitry of each level of performance and reliability. (1,2,3) Pin Configurations 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 I/O9R 33 11 I/O7L I/O10R 34 10 I/O6L I/O11R 35 9 I/O5L I/O12R 36 8 I/O4L I/O13R 37 7 I/O3L I/O14R 38 6 I/O2L GND 39 5 GND I/O15R 40 I/O1L 4 OER 41 3 I/O0L 7024 42 R/WR (4) 2 OEL PLG84 GND 43 1 VCC SEMR 44 84-Pin PLCC 84 R/WL CER 45 83 Top View SEML UBR 46 82 CEL LBR 47 81 UBL N/C 48 80 LBL A11R 49 79 N/C A10R 50 78 A11L A9R 51 77 A10L A8R 52 A9L 76 A7R 53 75 A8L 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 2740 drw 02J 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 A8L 75 53 A7R A9L 76 A8R 52 A10L 77 51 A9R A11L 78 A10R 50 N/C 79 49 A11R LBL 80 48 N/C UBL 81 47 LBR CEL 82 46 UBR SEML 83 45 CER R/WL 84 7024 44 SEMR (4) VCC 1 FP84 43 GND OEL 2 42 R/WR 84-Pin Flatpack I/O0L 3 41 OER Top View I/O1L 4 NOTES: 40 I/O15R GND 5 39 1. All VCC pins must be connected to the power supply. GND I/O2L 6 2. All GND pins must be connected to the ground supply. 38 I/O14R I/O3L 7 37 I/O13R 3. PLG84 package body is approximately 1.15 in x 1.15 in x .17 in. I/O4L 8 36 I/O12R FP84 package body is approximately 1.17 in x 1.17 in x .11 in. I/O5L 9 35 I/O11R 4. This package code is used to reference the package diagram. I/O6L 10 I/O10R 34 I/O7L 11 33 I/O9R 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 2740 drw 02F 6.422 Feb.20.20 A6R I/O8R A5R I/O7R A4R I/O6R A3R I/O5R A2R I/O4R I/O3R A1R A0R VCC INTR I/O2R BUSYR I/O1R M/S I/O0R GND GND BUSYL VCC INTL I/O15L A0L I/O14L A1L GND A2L I/O13L A3L I/O12L A4L I/O11L A5L I/O10L A6L I/O9L A7L I/O8L I/O8L A7L I/O9L A6L I/O10L A5L I/O11L A4L I/O12L A3L I/O13L A2L GND A1L I/O14L A0L I/O15L INTL VCC BUSYL GND GND I/O0R M/S I/O1R BUSYR I/O2R INTR VCC A0R I/O3R A1R I/O4R A2R I/O5R A3R I/O6R A4R I/O7R A5R I/O8R A6R