CY7C1460KV25-200BZXI Infineon

CY7C1460KV25/CY7C1462KV25 CY7C1460KVE25/CY7C1462KVE25 36-Mbit (1M 36/2M 18) Pipelined SRAM with NoBL Architecture (With ECC) 36-Mbit (1M 36/2M 18) Pipelined SRAM with NoBL Architecture (With ECC) Features Functional Description The CY7C1460KV25/CY7C1462KV25/CY7C1460KVE25/ Pin-compatible and functionally equivalent to ZBT CY7C1462KVE25 are 2.5 V, 1M 36/2M 18 synchronous Supports 250 MHz bus operations with zero wait states pipelined burst SRAMs with No Bus Latency (NoBL) logic, respectively. They are designed to support unlimited true Available speed grades are 250 MHz, 200 MHz, and 167 MHz back-to-back read/write operations with no wait states. The Internally self-timed output buffer control to eliminate the need CY7C1460KV25/CY7C1462KV25/CY7C1460KVE25/ to use asynchronous OE CY7C1462KVE25 are equipped with the advanced NoBL logic required to enable consecutive read/write operations with data Fully registered (inputs and outputs) for pipelined operation being transferred on every clock cycle. This feature dramatically Byte Write capability improves the throughput of data in systems that require frequent write/read transitions. The CY7C1460KV25/CY7C1462KV25/ 2.5 V core power supply CY7C1460KVE25/CY7C1462KVE25 are pin-compatible and functionally equivalent to ZBT devices. 2.5 V I/O power supply All synchronous inputs pass through input registers controlled by Fast clock-to-output times the rising edge of the clock. All data outputs pass through output 2.5 ns (for 250 MHz device) registers controlled by the rising edge of the clock. The clock ) signal, which when Clock enable (CEN) pin to suspend operation input is qualified by the clock enable (CEN deasserted suspends operation and extends the previous clock Synchronous self-timed writes cycle. Write operations are controlled by the byte write selects BW BW for CY7C1460KV25/CY7C1460KVE25 and CY7C1460KV25, CY7C1462KV25, CY7C1460KVE25 and a d BW for CY7C1462KV25/CY7C1462KVE25 and a write CY7C1462KVE25 available in JEDEC-standard Pb-free BW a b 100-pin TQFP, and Pb-free and non Pb-free 165-ball FBGA enable (WE) input. All writes are conducted with on-chip packages. synchronous self-timed write circuitry. Three synchronous chip enables (CE , CE , CE ) and an IEEE 1149.1 JTAG-Compatible Boundary Scan 1 2 3 ) provide for easy bank asynchronous output enable (OE Burst capability linear or interleaved burst order selection and output three-state control. In order to avoid bus contention, the output drivers are synchronously three-stated ZZ sleep mode option during the data portion of a write sequence. On-chip error correction code (ECC) to reduce soft error rate (SER) Selection Guide Description 250 MHz 200 MHz 167 MHz Unit Maximum access time 2.5 3.2 3.4 ns Maximum operating current 18 220 190 170 mA 36 240 210 190 Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-66679 Rev. *J Revised February 7, 2018 CY7C1460KV25/CY7C1462KV25 CY7C1460KVE25/CY7C1462KVE25 Logic Block Diagram CY7C1460KV25 ADDRESS A0, A1, A REGISTER 0 A1 A1 D1 Q1 A0 BURST A0 D0 Q0 MODE LOGIC ADV/LD CLK C C CEN WRITE ADDRESS WRITE ADDRESS REGISTER 1 REGISTER 2 O O S U D U T E T A P N P U T U S T ADV/LD A T WRITE REGISTRY E R MEMORY AND DATA COHERENCY S B BWa WRITE E DQs ARRAY CONTROL LOGIC G U DRIVERS A T DQPa BWb I F BWc E DQPb M S F BWd T E DQPc P E E R R DQPd S WE R S I S E N E G INPUT INPUT E E REGISTER 1 REGISTER 0 OE READ LOGIC CE1 CE2 CE3 SLEEP ZZ CONTROL Logic Block Diagram CY7C1462KV25 ADDRESS A0, A1, A REGISTER 0 A1 A1 D1 Q1 A0 BURST A0 D0 Q0 MODE LOGIC ADV/LD CLK C C CEN WRITE ADDRESS WRITE ADDRESS REGISTER 1 REGISTER 2 O O U U T T P S P D U E U A ADV/LD T N T T WRITE REGISTRY S A R MEMORY E B AND DATA COHERENCY BWa WRITE E DQs ARRAY U S CONTROL LOGIC G DRIVERS A F DQPa T I M E F BWb S DQPb P E E T S R R E S I R N WE S G E E INPUT INPUT E E REGISTER 1 REGISTER 0 OE READ LOGIC CE1 CE2 CE3 Sleep ZZ Control Document Number: 001-66679 Rev. *J Page 2 of 32