TM
CMOS BUS-MATCHING SyncFIFO IDT723623
256 x 36, 512 x 36, 1,024 x 36 IDT723633
IDT723643
Reset clears data and configures FIFO, Partial Reset clears data
FEATURES:
but retains configuration settings
Memory storage capacity:
Mailbox bypass registers for each FIFO
IDT723623 256 x 36
Free-running CLKA and CLKB may be asynchronous or
IDT723633 512 x 36
coincident (simultaneous reading and writing of data on a single
IDT723643 1,024 x 36
clock edge is permitted)
Clocked FIFO buffering data from Port A to Port B
Easily expandable in width and depth
Clock frequencies up to 83 MHz (8 ns access time)
Auto power down minimizes power dissipation
IDT Standard timing (using EF and FF) or First Word Fall
Available in a space-saving 128-pin Thin Quad Flatpack (TQFP)
Through Timing (using OR and IR flag functions)
Industrial temperature range (40C to +85C) is available
Programmable Almost-Empty and Almost-Full flags; each has
Green parts available, see ordering information
three default offsets (8, 16 and 64)
Serial or parallel programming of partial flags
DESCRIPTION:
Port B bus sizing of 36 bits (long word), 18 bits (word) and 9 bits
(byte) The IDT723623/723633/723643 are monolithic, high-speed, low-power,
Big- or Little-Endian format for word and byte bus sizes CMOS unidirectional Synchronous (clocked) FIFO memories which support
FUNCTIONAL BLOCK DIAGRAM
MBF1
Mail 1
Register
CLKA
CSA Port-A
W/RA Control
Logic
ENA
MBA
RAM ARRAY 36
36
36
FIFO1 256 x 36
RS1
Mail1, 512 x 36
RS2
Mail2,
1,024 x 36
Reset
PRS
Logic
36
Write
Read
Pointer
Pointer
A0-A35
B0-B35
Status Flag EF/OR
FF/IR
Logic
AF AE
36
36
SPM
Programmable Flag
Timing
FS0/SD
FWFT
Offset Registers
Mode
FS1/SEN
10
CLKB
CSB
W/RB
Port-B
ENB
Control
MBB
Logic
BE
BM
Mail 2
SIZE
Register
3269 drw01
MBF2
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. SyncFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE FEBRUARY 2009
1
2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. DSC-3269/4
Input
Register
Bus-
Matching
Output
RegisterIDT723623/723633/723643 BUS-MATCHING SyncFIFO
256 x 36, 512 x 36, 1,024 x 36 COMMERCIAL TEMPERATURE RANGE
Communication between each port may bypass the FIFO via two mailbox
DESCRIPTION (CONTINUED)
registers. The mailbox registers' width matches the selected Port B bus width.
clock frequencies up to 83 MHz and have read access times as fast as 8 ns.
Each mailbox register has a flag (MBF1 and MBF2) to signal when new mail
The 256/512/1,024 x 36 dual-port SRAM FIFO buffers data from port A to port
has been stored.
B. FIFO data on Port B can output in 36-bit, 18-bit, or 9-bit formats with a choice
Two kinds of reset are available on these FIFOs: Reset and Partial Reset.
of Big- or Little-Endian configurations.
Reset initializes the read and write pointers to the first location of the memory
These devices are synchronous (clocked) FIFOs, meaning each port
array and selects serial flag programming, parallel flag programming, or one
employs a synchronous interface. All data transfers through a port are gated
of three possible default flag offset settings, 8, 16 or 64.
to the LOW-to-HIGH transition of a port clock by enable signals. The clocks for
Partial Reset also sets the read and write pointers to the first location of the
each port are independent of one another and can be asynchronous or
memory. Unlike Reset, any settings existing prior to Partial Reset (i.e.,
coincident. The enables for each port are arranged to provide a simple
programming method and partial flag default offsets) are retained. Partial Reset
bidirectional interface between microprocessors and/or buses with synchro-
nous control.
PIN CONFIGURATION
INDEX
W/RA 1 CLKB
102
2 Vcc
ENA 101
3 Vcc
CLKA 100
4
GND 99 B35
A35 5 B34
98
A34 6 B33
97
7 B32
A33 96
A32 8 95 GND
Vcc 9 GND
94
10 B31
A31 93
11
A30 92 B30
12
GND 91 B29
A29 13 90 B28
14 B27
A28 89
15 B26
A27 88
A26 16 87 Vcc
17 86 B25
A25
18 85 B24
A24
19
A23 84 BM
20 83 GND
BE/FWFT
21 82 B23
GND
22 81 B22
A22
23 80 B21
Vcc
A21 24 79 B20
25 78 B19
A20
26 77 B18
A19
76
A18 27 GND
28 75 B17
GND
29 74 B16
A17
30 73 SIZE
A16
A15 31 72 Vcc
32 71 B15
A14
33 70 B14
A13
69
Vcc 34 B13
68
35 B12
A12
36 67 GND
GND
37 66 B11
A11
38 65 B10
A10
3269 drw02
TQFP (PK128-1, order code: PF)
TOP VIEW
2
CSA
A9
39 128
FF/IR
A8
40 127
NC
A7 126
41
PRS
A6 125
42
Vcc
GND 43 124
AF
A5 44 123
NC
A4 122
45
MBF2
A3 46 121
MBA
SPM 47 120
RS1
Vcc 48 119
FS0/SD
A2 118
49
117 GND
A1 50
GND
A0 116
51
FS1/SEN
GND 52 115
B0 114 RS2
53
MBB
B1 54 113
MBF1
B2 55 112
B3 111 Vcc
56
B4 110 AE
57
109 NC
B5 58
EF/OR
GND 108
59
B6 107 NC
60
106
Vcc 61 GND
105 CSB
B7 62
B8 104 W/RB
63
103 ENB
B9 64