IDT7280 CMOS DUAL ASYNCHRONOUS FIFO IDT7281 IDT7282 DUAL 256 x 9, DUAL 512 x 9, IDT7283 DUAL 1,024 x 9, DUAL 2,048 x 9, IDT7284 DUAL 4,096 x 9, DUAL 8,192 x 9 IDT7285 LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018 DESCRIPTION: FEATURES: The IDT7280 is equivalent to two IDT7200 256 x 9 FIFOs The IDT7280/7281/7282/7283/7284/7285 are dual-FIFO memories that The IDT7281 is equivalent to two IDT7201 512 x 9 FIFOs load and empty data on a first-in/first-out basis. These devices are functional The IDT7282 is equivalent to two IDT7202 1,024 x 9 FIFOs and compatible to two IDT7200/7201/7202/7203/7204/7205 FIFOs in a single The IDT7283 is equivalent to two IDT7203 2,048 x 9 FIFOs package with all associated control, data, and flag lines assigned to separate The IDT7284 is equivalent to two IDT7204 4,096 x 9 FIFOs pins. The devices use Full and Empty flags to prevent data overflow and The IDT7285 is equivalent to two IDT7205 8,192 x 9 FIFOs underflow and expansion logic to allow for unlimited expansion capability in both Low power consumption word size and depth. Active: 685 mW (max.) The reads and writes are internally sequential through the use of ring pointers, Power-down: 83 mW (max.) with no address information required to load and unload data. Data is toggled Ultra high speed12 ns access time in and out of the devices through the use of the Write (W) and Read (R) pins. Asynchronous and simultaneous read and write The devices utilize a 9-bit wide data array to allow for control and parity bits Offers optimal combination of data capacity, small foot print at the users option. This feature is especially useful in data communications and functional flexibility applications where it is necessary to use a parity bit for transmission/reception Ideal for bi-directional, width expansion, depth expansion, error checking. It also features a Retransmit (RT) capability that allows for reset bus-matching, and data sorting applications of the read pointer to its initial position when RT is pulsed LOW to allow for Status Flags: Empty, Half-Full, Full retransmission from the beginning of data. A Half-Full Flag is available in the Auto-retransmit capability single device mode and width expansion modes. High-performance CMOS technology These FIFOs are fabricated using high-speed CMOS technology. They are Space-saving TSSOP designed for those applications requiring asynchronous and simultaneous Industrial temperature range (40C to +85C) is available read/writes in multiprocessing and rate buffer applications. FUNCTIONAL BLOCK DIAGRAM DATA INPUTS DATA INPUTS (DA0 -DA8 ) RSA (DB0 -DB8 ) RSB WB WRITE RAM WRITE RAM WA ARRAY A CONTROL CONTROL ARRAY B 256 x 9 256 x 9 512 x 9 512 x 9 1,024 x 9 1,024 x 9 WRITE WRITE 2,048 x 9 READ READ 2,048 x 9 POINTER 4,096 x 9 POINTER 4,096 x 9 POINTER POINTER 8,192 x 9 8,192 x 9 THREE- THREE- STATE STATE BUFFERS BUFFERS READ READ RA RESET RESET CONTROL CONTROL LOGIC LOGIC FLAG FLAG LOGIC LOGIC EXPANSION EXPANSION LOGIC LOGIC XIA XOA/HFA FFA EFA DATA FLA/RTA RB XIB XOB/HFB FFB EFB FLB/RTB DATA OUTPUTS OUTPUTS 3208 drw 01 (QA0 -QA8 ) (QB0 -QB8 ) IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES NOVEMBER 2017 1 2017 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. DSC-3208/10IDT7280/7281/7282/7283/7284/7285 5V ASYNCHRONOUS FIFO DUAL 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9 COMMERCIAL TEMPERATURE RANGE PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS Symbol Rating Com l & Ind l Unit 1 FFA 56 XIA VTERM Terminal Voltage with 0.5 to +7.0 V 2 QA0 55 DA0 Respect to GND 3 QA1 54 DA1 TSTG Storage Temperature 55 to +125 C 4 QA2 53 DA2 5 QA3 52 DA3 IOUT DC Output Current 50 to +50 mA 6 QA8 51 DA8 NOTE: 7 GND 50 WA 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause RA 8 VCC 49 permanent damage to the device. This is a stress rating only and functional operation 9 QA4 48 DA4 of the device at these or any other conditions above those indicated in the operational QA5 10 DA5 47 sections of this specification is not implied. Exposure to absolute maximum rating 11 QA6 46 DA6 conditions for extended periods may affect reliability. 12 QA7 45 DA7 XOA/HFA 13 FLA/RTA 44 EFA 14 RSA 43 RECOMMENDED DC OPERATING FFB 15 XIB 42 QB0 16 DB0 41 CONDITIONS QB1 17 DB1 40 Symbol Parameter Min. Typ. Max. Unit QB2 18 DB2 39 QB3 19 DB3 38 VCC Supply Voltage 4.5 5.0 5.5 V QB8 20 37 DB8 GND Supply Voltage 0 0 0 V GND 21 WB 36 (1) RB 22 VCC 35 VIH Input High Voltage 2.0 V QB4 DB4 23 34 (2) VIL Input Low Voltage 0.8 V QB5 24 DB5 33 QB6 DB6 25 32 TA Operating Temperature 0 70 C QB7 26 DB7 31 Commercial XOB/HFB 27 FLB/RTB 30 EFB RSB 28 29 TA Operating Temperature 40 85 C 3208 drw 02 Industrial NOTES: TSSOP (SO56-2, order code: PA) 1. For RT/RS/XI input, VIH = 2.6V (commercial). TOP VIEW 2. 1.5V undershoots are allowed for 10ns once per cycle. DC ELECTRICAL CHARACTERISTICS (Commercial: VCC = 5V 10%, TA = 0C to +70C Industrial: VCC = 5V 10%, TA = 40C to +85C) IDT7280L IDT7283L IDT7281L IDT7284L IDT7282L IDT7285lL (1) (1) Commercial & Industrial Commercial & Industrial tA = 12, 15 ns tA = 12, 15 ns Symbol Parameter Min. Max. Min. Max. Unit (2) ILI Input Leakage Current (Any Input) 1 1 1 A (3) ILO Output Leakage Current 10 10 10 10 A VOH Output Logic 1 Voltage IOH = 2mA 2.4 2.4 V VOL Output Logic 0 Voltage IOL = 8mA 0.4 0.4 V (4,5) (6) ICC1 Active Power Supply Current (both FIFOs) 125 150 mA (4,7) ICC2 Standby Current (R=W=RS=FL/RT=VIH) 15 15 mA NOTES: 1. Industrial temperature range product for the 15ns speed grade is available as a standard AC TEST CONDITIONS device. Input Pulse Levels GND to 3.0V 2. Measurements with 0.4 VIN VCC. 3. R VIH, 0.4 VOUT VCC. Input Rise/Fall Times 5ns 4. Tested with outputs open (IOUT = 0). Input Timing Reference Levels 1.5V 5. Tested at f = 20 MHz. o Output Reference Levels 1.5V 6. Typical ICC1 = 2* 15 + 2*fS + 0.02*CL*fS (in mA) with VCC = 5V, TA = 25 C, fS = WCLK frequency = RCLK frequency (in MHz, using TTL levels), data switching at fS/2, Output Load See Figure 1 CL = capacitive load (in pF). 7. All Inputs = VCC - 0.2V or GND + 0.2V. 5V 1.1K TO OUTPUT o CAPACITANCE (TA = +25 C, f = 1.0 MHz) PIN 30pF* Symbol Parameter Condition Max. Unit 680 CIN Input Capacitance VIN = 0V 8 pF 3208 drw 03 COUT Output Capacitance VOUT = 0V 8 pF or equivalent circuit NOTE: Figure 1. Output Load 1. Characterized values, not currently tested. * Includes scope and jig capacitances. 2 JUNE 29, 2012