728985JG8 Renesas

TIME SLOT INTERCHANGE IDT728980 DIGITAL SWITCH 256 x 256 and output channels. Those 256 channels are divided into 8 serial inputs and FEATURES: outputs, each of which consists of 32 channels (64 Kbit/s per channel) to form 256 x 256 channel non-blocking switch a multiplexed 2.048 Mb/s stream. Serial Telecom Bus Compatible (ST-BUS ) 8 RX inputs32 channels at 64 Kbit/s per serial line FUNCTIONAL DESCRIPTION 8 TX output32 channels at 64 Kbit/s per serial line Three-state serial outputs A functional block diagram of the IDT728980 device is shown on below. The Microprocessor Interface (8-bit data bus) serial ST-BUS streams operate continuously at 2.048 Mb/s and are arranged 5V Power Supply in 125s wide frames each containing 32, 8-bit channels. Eight input (RX0-7) Available in 44-pin Plastic Leaded Chip Carrier (PLCC) and eight output (TX0-7) serial streams are provided in the IDT728980 device Operating Temperature Range -40C to +85C allowing a complete 256 x 256 channel non-blocking switch matrix to be constructed. The serial interface clock (C4i) for the device is 4.096 MHz. The received serial data is internally converted to a parallel format by the on chip serial-to-parallel converters and stored sequentially in a 256-position Data DESCRIPTION: Memory. By using an internal counter that is reset by the input 8 KHz frame pulse, The IDT728980 is a ST-BUS compatible digital switch controlled by a F0i, the incoming serial data streams can be framed and sequentially addressed. microprocessor. The IDT728980 can handle as many as 256, 64 Kbit/s input FUNCTIONAL BLOCK DIAGRAM ODE C4i F0i VCC GND TX0 Timing RX0 Unit Output MUX TX1 RX1 TX2 RX2 Receive Transmit TX3 RX3 Data Serial Data Serial Data Streams Memory Streams RX4 TX4 RX5 TX5 Connection Control Register Memory RX6 TX6 RX7 Microprocessor Interface TX7 5706 drw01 CCO DS A0/ CS R/W D0/ DTA A5 D7 MARCH 2017 IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. 1 2017 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. DSC-5706/2IDT728980 Time Slot Interchange Digital Switch COMMERCIAL TEMPERATURE RANGE 256 x 256 PIN CONFIGURATION INDEX RX3 7 TX3 39 RX4 8 38 TX4 RX5 9 37 TX5 RX6 10 36 TX6 35 RX7 11 TX7 VCC 34 12 GND 33 13 F0i D0 32 C4i 14 D1 A0 15 31 D2 A1 16 30 D3 A2 17 29 D4 5706 drw02 NOTE: 1. DNC - Do Not Connect. PLCC: 0.05in. pitch, 0.65in. x 0.65in. (J44, order code: J) TOP VIEW PIN DESCRIPTIONS SYMBOL NAME I/O DESCRIPTION GND Ground. Ground Rail. VCC VCC +5.0 Volt Power Supply. DTA Data Acknowledgment O This active LOW output indicates that a data bus transfer is complete. A pull-up resistor is required at this (Open Drain) output. RX0-7 RX Input 0 to 7 I Serial data input streams. These streams have 32 channels at data rates of 2.048 Mb/s. F0i Frame Pulse I This input identifies frame synchronization signals formatted to ST-BUS specifications. C4i Clock I 4.096 MHz serial clock for shifting data in and out of the data streams. A0-A5 Address 0 to 5 I These lines provide the address to IDT728980 internal registers. DS Data Strobe I This is the input for the active HIGH data strobe on the microprocessor interface. This input operates with CS to enable the internal read and write generation. R/W Read/Write I This input controls the direction of the data bus lines (D0-D7) during a microprocessor access. CS Chip Select I Active LOW input enabling a microprocessor read or write of control register or internal memories. D0-D7 Data Bus 0 to 7 I/O These pins provide microprocessor access to data in the internal control register. Connection Memory HIGH, Connection Memory LOW and data memory. TX0-7 TX Outputs 0 to 7 O Serial data output streams. These streams are composed of 32, 64 Kbit/s channels at data rates of 2.048 Mb/s. (Three-state Outputs) ODE Output Drive Enable I This is an output enable for the TX0-7 serial outputs. If this input is LOW, TX0-7 are high-impedance. If this is HIGH, each channel may still be put into high-impedance by software control. CCO Control Channel Output O This output is a 2.048 Mb/s line which contains 256 bits per frame. The level of each bit is controlled by the contents of the CCO bit in the Connection Memory HIGH locations. 2 6 (1) DNC(1) DNC 18 5 RX2 A3 19 4 RX1 A4 20 3 RX0 A5 21 2 DTA 22 DS 1 CCO 23 R/W 44 ODE CS 24 43 TX0 D7 25 42 TX1 26 D6 41 TX2 D5 27 40 DNC(1) (1) DNC 28