2.5 VOLT HIGH-SPEED TeraSync FIFO *IDT72T1845, *IDT72T1855 18-BIT/9-BIT CONFIGURATIONS *IDT72T1865, *IDT72T1875 2,048 x 18/4,096 x 9, 4,096 x 18/8,192 x 9, 8,192 x 18/16,384 x 9, *IDT72T1885, *IDT72T1895 16,384 x 18/32,768 x 9, 32,768 x 18/65,536 x 9, 65,536 x 18/131,072 x 9, IDT72T18105, IDT72T18115 131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9, 524,288 x 18/1,048,576 x 9 IDT72T18125 *SPECIFIED PRODUCTS ARE EOL - LAST TIME BUY EXPIRES MAY 26, 2018 Separate SCLK input for Serial programming of flag offsets FEATURES: User selectable input and output port bus-sizing Choose among the following memory organizations: - x9 in to x9 out IDT72T1845 2,048 x 18/4,096 x 9 - x9 in to x18 out IDT72T1855 4,096 x 18/8,192 x 9 - x18 in to x9 out IDT72T1865 8,192 x 18/16,384 x 9 - x18 in to x18 out IDT72T1875 16,384 x 18/32,768 x 9 Big-Endian/Little-Endian user selectable byte representation IDT72T1885 32,768 x 18/65,536 x 9 Auto power down minimizes standby power consumption IDT72T1895 65,536 x 18/131,072 x 9 Master Reset clears entire FIFO IDT72T18105 131,072 x 18/262,144 x 9 Partial Reset clears data, but retains programmable settings IDT72T18115 262,144 x 18/524,288 x 9 Empty, Full and Half-Full flags signal FIFO status IDT72T18125 524,288 x 18/1,048,576 x 9 Select IDT Standard timing (using EF and FF flags) or First Word Up to 225 MHz Operation of Clocks Fall Through timing (using OR and IR flags) User selectable HSTL/LVTTL Input and/or Output Output enable puts data outputs into high impedance state Read Enable & Read Clock Echo outputs aid high speed operation JTAG port, provided for Boundary Scan function User selectable Asynchronous read and/or write port timing Available in 144-pin (13mm x 13mm) or 240-pin (19mm x 19mm) 2.5V LVTTL or 1.8V, 1.5V HSTL Port Selectable Input/Ouput voltage Plastic Ball Grid Array (PBGA) 3.3V Input tolerant Easily expandable in depth and width Mark & Retransmit, resets read pointer to user marked position Independent Read and Write Clocks (permit reading and writing Write Chip Select (WCS) input enables/disables Write operations simultaneously) Read Chip Select (RCS) synchronous to RCLK High-performance submicron CMOS technology Programmable Almost-Empty and Almost-Full flags, each flag can Industrial temperature range (40C to +85C) is available default to one of eight preselected offsets Green parts are available, see ordering information Program programmable flags by either serial or parallel means For IDT72T1845/55/65/75/85/95 functional replacement device use Selectable synchronous/asynchronous timing modes for Almost- IDT72T18125 Empty and Almost-Full flags FUNCTIONAL BLOCK DIAGRAM D0 -Dn (x18 or x9) LD SEN SCLK WEN WCLK/WR WCS INPUT REGISTER OFFSET REGISTER FF/IR PAF WRITE CONTROL ASYW EF/OR LOGIC FLAG PAE RAM ARRAY HF LOGIC 2,048 x 18 or 4,096 x 9 FWFT/SI 4,096 x 18 or 8,192 x 9 WRITE POINTER PFM 8,192 x 18 or 16,384 x 9 FSEL0 16,384 x 18 or 32,768 x 9 FSEL1 32,768 x 18 or 65,536 x 9 65,536 x 18 or 131,072 x 9 131,072 x 18 or 262,144 x 9 BE CONTROL READ POINTER 262,144 x 18 or 524,288 x 9 LOGIC IP 524,288 x 18 or 1,048,576 x 9 IW BUS CONFIGURATION OW READ RT CONTROL MARK MRS OUTPUT REGISTER RESET LOGIC ASYR LOGIC PRS TCK TRST JTAG CONTROL RCLK/RD TMS (BOUNDARY SCAN) REN TDO RCS TDI Vref WHSTL HSTL I/0 EREN OE RHSTL 5909 drw01 CONTROL SHSTL Q0 -Qn (x18 or x9) ERCLK IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. TeraSync FIFO is a trademark of Integrated Device Technology, Inc. COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES MAY 2017 1 DSC-5909/20COMMERCIAL AND INDUSTRIAL IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/ 8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9 TEMPERATURE RANGES PIN CONFIGURATIONS A1 BALL PAD CORNER A WCS PRS LD FF/IR OW HF BE IP ASYR PFM EREN MARK B WCLK MRS FWFT/SI PAF FSEL0 SHSTL FSEL1 DNC RHSTL PAE EF/OR RCLK C WHSTL WEN VDDQ VDDQ VDDQ VCC VCC VDDQ VDDQ VDDQ REN RT D ASYW SEN VDDQ VCC VCC GND GND VCC VCC VDDQ RCS OE E IW VCC GND GND GND GND GND VCC VDDQ SCLK VDDQ Q17 F D17 VREF VCC GND GND VCC VDDQ Q16 GND GND GND GND G D15 D16 VCC VCC VDDQ Q15 GND GND GND GND GND GND H D13 D14 VDDQ GND GND GND GND VDDQ Q14 VCC VCC Q13 J D11 D12 VDDQ VCC VDDQ Q12 Q11 VCC GND GND VCC VCC K D9 D10 VDDQ VDDQ VCC VCC VDDQ VDDQ VDDQ Q10 Q9 VDDQ L D7 D5 D3 D1 TCK TDI ERCLK Q1 Q3 Q5 Q8 TRST M D6 D4 D2 D0 TMS TD0 Q0 Q2 Q4 Q6 Q7 D8 1 2 3 456 7 8 9 10 11 12 5909 drw02 NOTE: 1. DNC - Do Not Connect. IDT72T1845/72T1855/72T1865/72T1875/72T1885/72T1895 Only PBGA: 1mm pitch, 13mm x 13mm BB144 (Order code: BB) TOP VIEW 2