TM 2.5V 18M-BIT HIGH-SPEED TeraSync FIFO 36-BIT CONFIGURATIONS IDT72T36135M 524,288 x 36 Separate SCLK input for Serial programming of flag offsets FEATURES: Auto power down minimizes standby power consumption Industrys largest FIFO memory organization: Master Reset clears entire FIFO IDT72T36135 524,288 x 36 - 18M-bits Partial Reset clears data, but retains programmable settings Up to 200 MHz Operation of Clocks Empty and Full flags signal FIFO status Functionally and pin compatible to 9Mbit IDT72T36125 TeraSync Select IDT Standard timing (using EF 1:2 and FF 1:2 flags) or First devices Word Fall Through timing (using OR 1:2 and IR 1:2 flags) User selectable HSTL/LVTTL Input and/or Output Output enable puts data outputs into high impedance state User selectable Asynchronous read and/or write port timing JTAG port, provided for Boundary Scan function Mark & Retransmit, resets read pointer to user marked position Available in 240-pin (19mm x 19mm)Plastic Ball Grid Array (PBGA) Write Chip Select (WCS) input disables Write Port 50% more space saving than the leading 9M-bit FIFOs Read Chip Select (RCS) synchronous to RCLK Independent Read and Write Clocks (permit reading and writing Programmable Almost-Empty and Almost-Full flags, each flag can simultaneously) default to one of eight preselected offsets High-performance submicron CMOS technology Program programmable flags by either serial or parallel means Industrial temperature range (40C to +85C) is available Selectable synchronous/asynchronous timing modes for Almost- Green parts available, see ordering information Empty and Almost-Full flags FUNCTIONAL BLOCK DIAGRAM D0 -Dn (x36) LD SEN SCLK WEN WCLK/WR WCS INPUT REGISTER OFFSET REGISTER FF/IR 1:2 WRITE CONTROL PAF 1:2 ASYW EF/OR 1:2 LOGIC FLAG PAE 1:2 LOGIC FWFT/SI WRITE POINTER PFM RAM ARRAY FSEL0 524,288 x 36 FSEL1 MRS READ POINTER RESET LOGIC PRS TCK TRST JTAG CONTROL TMS RT READ (BOUNDARY TDO CONTROL MARK SCAN) OUTPUT REGISTER LOGIC ASYR TDI Vref WHSTL HSTL I/0 RHSTL CONTROL RCLK/RD SHSTL REN RCS 6723 drw01 OE Q0 -Qn (x36) IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The TeraSync FIFO is a trademark of Integrated Device Technology, Inc. COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES MAY 2016 1 2016 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. DSC-6723/5IDT72T36135M 2.5V 18M-BIT TeraSync 36-BIT FIFO COMMERCIAL AND INDUSTRIAL 524,288 x 36 TEMPERATURE RANGES PIN CONFIGURATION A1 BALL PAD CORNER A VCC VCC WCLK GND FF1 VDDQ VDDQ VDDQ VDDQ VDDQ VCC VCC VCC VCC PRS FF2 RCLK OE B VCC VCC VCC VCC VCC VCC GND EF1 VDDQ VDDQ VDDQ VDDQ VDDQ WEN MRS PAF1 REN RCS C VCC VCC VCC VCC VCC VCC WCS LD GND PAF2 PAE1 MARK RT VDDQ VDDQ VDDQ VDDQ VDDQ D VCC VCC VCC FWFT/SI FSEL0 SHSTL FSEL1 GND GND EF2 RHSTL PFM VDDQ VDDQ VDDQ DNC PAE2 ASYR E VCC VCC VCC GND GND VDDQ VDDQ VDDQ F VCC VCC VCC GND GND VDDQ VDDQ VDDQ G VCC SCLK WHSTL GND VDDQ VDDQ VDDQ SEN H VCC VCC VCC GND VDDQ VDDQ VDDQ ASYW GND GND GND GND J VCC VCC VCC VREF GND VDDQ VDDQ VDDQ GND GND GND GND K VCC VCC VCC DNC GND VDDQ VDDQ VDDQ GND GND GND GND L D33 D34 D35 GND GND VDDQ Q35 Q34 GND GND GND GND M D30 D31 D32 GND GND Q33 Q32 Q31 N D27 D28 D29 GND GND Q30 Q29 Q28 P D25 Q27 Q25 D24 D26 GND GND Q26 R D21 D22 D23 GND GND GND GND GND GND GND GND GND GND GND GND Q24 Q23 Q22 T D19 D20 D13 D10 D5 D4 D1 TMS TDO GND Q0 Q2 Q3 Q8 Q11 Q14 Q21 Q20 U D18 D17 D7 GND Q1 Q6 Q5 Q9 Q12 Q18 D14 D11 D8 D2 TRST TDI Q15 Q19 V VCC D16 D15 Q7 Q10 Q13 Q17 D12 D9 D6 D3 D0 TCK GND DNC Q4 Q16 VDDQ 12 3 4 56 7 8 9 10 11 12 13 14 15 16 17 18 6723 drw02 NOTE: 1. DNC - Do Not Connect. PBGA: 1mm pitch, 19mm x 19mm (BB240, order code: BB) TOP VIEW 2