TM 2.5 VOLT HIGH-SPEED TeraSync FIFO 72-BIT CONFIGURATIONS 16,384 x 72, 32,768 x 72, IDT72T7285, IDT72T7295, 65,536 x 72, 131,072 x 72 IDT72T72105, IDT72T72115 - x72 in to x72 out FEATURES: - x72 in to x36 out Choose among the following memory organizations: - x72 in to x18 out IDT72T7285 16,384 x 72 - x36 in to x72 out IDT72T7295 32,768 x 72 - x18 in to x72 out IDT72T72105 65,536 x 72 Big-Endian/Little-Endian user selectable byte representation IDT72T72115 131,072 x 72 Auto power down minimizes standby power consumption Up to 225 MHz Operation of Clocks Master Reset clears entire FIFO User selectable HSTL/LVTTL Input and/or Output Partial Reset clears data, but retains programmable settings Read Enable & Read Clock Echo outputs aid high speed operation Empty, Full and Half-Full flags signal FIFO status User selectable Asynchronous read and/or write port timing Select IDT Standard timing (using EF and FF flags) or First Word 2.5V LVTTL or 1.8V, 1.5V HSTL Port Selectable Input/Ouput voltage Fall Through timing (using OR and IR flags) 3.3V Input tolerant Output enable puts data outputs into high impedance state Mark & Retransmit, resets read pointer to user marked position JTAG port, provided for Boundary Scan function Write Chip Select (WCS) input disables Write Port HSTL inputs Available in 324-pin (19mm x 19mm)Plastic Ball Grid Array (PBGA) Read Chip Select (RCS) synchronous to RCLK Easily expandable in depth and width Programmable Almost-Empty and Almost-Full flags, each flag can Independent Read and Write Clocks (permit reading and writing default to one of eight preselected offsets simultaneously) Program programmable flags by either serial or parallel means High-performance submicron CMOS technology Selectable synchronous/asynchronous timing modes for Almost- Industrial temperature range (40C to +85C) is available Empty and Almost-Full flags Green parts are available, see ordering information Separate SCLK input for Serial programming of flag offsets User selectable input and output port bus-sizing FUNCTIONAL BLOCK DIAGRAM D0 -Dn (x72, x36 or x18) LD SEN SCLK WEN WCLK/WR WCS INPUT REGISTER OFFSET REGISTER FF/IR PAF WRITE CONTROL ASYW EF/OR LOGIC FLAG PAE HF LOGIC FWFT/SI RAM ARRAY WRITE POINTER PFM 16,384 x 72 FSEL0 32,768 x 72 FSEL1 65,536 x 72 BE CONTROL READ POINTER 131,072 x 72 LOGIC IP BM BUS IW CONFIGURATION OW RT READ MARK CONTROL MRS RESET OUTPUT REGISTER LOGIC ASYR LOGIC PRS TCK TRST JTAG CONTROL RCLK/RD TMS (BOUNDARY SCAN) REN TDO RCS TDI Vref WHSTL HSTL I/0 EREN OE RHSTL 5994 drw01 CONTROL SHSTL Q0 -Qn (x72, x36 or x18) ERCLK IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The TeraSync FIFO is a trademark of Integrated Device Technology, Inc. JUNE 2017 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES 1 2017 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. DSC-5994/16 IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync 72-BIT FIFO COMMERCIAL AND INDUSTRIAL 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72 TEMPERATURE RANGES PIN CONFIGURATION A1 BALL PAD CORNER A PRS FF EREN OE VCC D60 D61 D63 D66 D69 WCLK GND RCLK Q69 Q66 Q64 Q63 VDDQ B D59 D58 D62 D64 D67 D70 WEN MRS GND PAF EF REN RCS Q70 Q67 Q65 Q61 Q62 C D57 D56 D55 D65 D68 D71 LD GND HF PAE MARK RT Q71 Q68 Q58 Q59 Q60 WCS D D54 D53 D52 FWFT/SI OW FS0 SHSTL FS1 GND BE IP BM RHSTL ASYR PFM Q55 Q56 Q57 E D51 D50 D49 VCC VCC VCC VCC VCC GND GND VDDQ VDDQ VDDQ VDDQ VDDQ Q52 Q53 Q54 F D48 D47 D46 VCC VCC VCC VCC VCC GND GND VDDQ VDDQ VDDQ VDDQ VDDQ Q49 Q50 Q51 G D45 SEN SCLK WHSTL VCC VCC GND GND GND GND GND GND VDDQ VDDQ VDDQ Q46 Q47 Q48 H D44 D43 D42 ASYW VCC VCC GND GND GND GND GND GND VDDQ VDDQ VDDQ Q43 Q44 Q45 J D41 D40 D39 VREF VCC VCC GND GND GND GND GND GND VDDQ VDDQ Q40 Q41 Q42 VDDQ K D36 D37 D38 IW VCC VCC GND GND GND GND GND GND VDDQ VDDQ Q39 Q38 Q37 VDDQ L D33 D34 D35 VCC VCC VCC GND GND GND GND GND GND VDDQ VDDQ VDDQ Q36 Q35 Q34 M D30 D31 D32 VCC VCC VCC GND GND GND GND GND GND VDDQ VDDQ VDDQ Q33 Q32 Q31 N D27 D28 D29 VCC VCC VCC VCC VCC GND GND VDDQ VDDQ VDDQ VDDQ VDDQ Q30 Q29 Q28 P D24 D25 D26 VCC VCC VCC VCC VCC GND GND VDDQ VDDQ VDDQ VDDQ VDDQ Q27 Q26 Q25 R D22 D21 D23 VCC VCC VCC VCC VCC GND GND VDDQ VDDQ VDDQ VDDQ VDDQ Q24 Q23 Q22 T D19 D20 D13 D10 D5 D4 D1 TMS TDO GND Q0 Q2 Q3 Q8 Q11 Q14 Q21 Q20 U D18 D17 D14 D11 D7 D8 D2 TDI GND Q1 Q6 Q5 Q9 Q12 Q15 Q18 Q19 TRST V VCC D16 D15 D12 D9 D6 D3 D0 TCK GND ERCLK Q4 Q7 Q10 Q13 Q16 Q17 VDDQ 12 34 56 7 8 9 10 11 12 13 14 15 16 17 18 5994 drw02 PBGA: 1mm pitch, 19mm x 19mm (BB324, BBG324) Order code: BB, BBG TOP VIEW 2