IDT72420 CMOS SyncFIFO IDT72200 64 x 8, 256 x 8, IDT72210 512 x 8, 1,024 x 8, IDT72220 IDT72230 2,048 x 8 and 4,096 x 8 IDT72240 LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018 FEATURES: DESCRIPTION: 64 x 8-bit organization (IDT72420) The IDT72420/72200/72210/72220/72230/72240 SyncFIFO are very 256 x 8-bit organization (IDT72200) high-speed, low-power First-In, First-Out (FIFO) memories with clocked read 512 x 8-bit organization (IDT72210) and write controls. These devices have a 64, 256, 512, 1,024, 2,048, and 4,096 1,024 x 8-bit organization (IDT72220) x 8-bit memory array, respectively. These FIFOs are applicable for a wide 2,048 x 8-bit organization (IDT72230) variety of data buffering needs, such as graphics, Local Area Networks (LANs), 4,096 x 8-bit organization (IDT72240) and interprocessor communication. 10 ns read/write cycle time (IDT72420/72200/72210/72220/72230/ These FIFOs have 8-bit input and output ports. The input port is controlled 72240) by a free-running clock (WCLK), and a Write Enable pin (WEN). Data is written Read and Write Clocks can be asynchronous or coincidental into the Synchronous FIFO on every clock when WEN is asserted. The output Dual-Ported zero fall-through time architecture port is controlled by another clock pin (RCLK) and a Read Enable pin (REN). Empty and Full flags signal FIFO status The Read Clock can be tied to the Write Clock for single clock operation or the Almost-Empty and Almost-Full flags set to Empty+7 and Full-7, two clocks can run asynchronous of one another for dual clock operation. An respectively Output Enable pin (OE) is provided on the read port for three-state control of Output enable puts output data bus in high-impedance state the output. Produced with advanced submicron CMOS technology These Synchronous FIFOs have two endpoint flags, Empty (EF) and Full Available in 28-pin 300 mil plastic DIP (FF). Two partial flags, Almost-Empty (AE) and Almost-Full (AF), are provided For surface mount product please see the IDT72421/72201/72211/ for improved system control. The partial (AE) flags are set to Empty+7 and Full- 72221/72231/72241 data sheet 7 for AE and AF respectively. Green parts available, see ordering information These FIFOs are fabricated using high-speed submicron CMOS technol- ogy. FUNCTIONAL BLOCK DIAGRAM D0 - D7 WCLK WEN INPUT REGISTER EF FLAG AE WRITE CONTROL LOGIC AF LOGIC FF RAM ARRAY 64 x 8, 256 x 8, WRITE POINTER READ POINTER 512 x 8, 1,024 x 8, 2,048 x 8, 4,096 x 8 READ CONTROL LOGIC OUTPUT REGISTER RESET LOGIC RCLK RS REN OE 2680 drw01 Q0 - Q7 IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The SyncFIFO is a trademark of Integrated Device Technology, Inc. COMMERCIAL TEMPERATURE RANGE FEBRUARY 2018 1 2018 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. DSC-2680/7IDT72420/72200/72210/72220/72230/72240 CMOS SYNCFIFO COMMERCIAL TEMPERATURE RANGE 64 x 8, 256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8, 4,096 x 8 PIN CONFIGURATION 1 28 D4 D5 D3 2 27 D6 D2 3 26 D7 D1 4 25 RS WEN D0 5 24 AF 6 23 WCLK AE 7 22 VCC GND 8 21 Q7 RCLK 9 20 Q6 REN 10 19 Q5 OE 11 18 Q4 EF Q3 12 17 FF Q2 13 16 Q0 Q1 14 15 2680 drw02 PLASTIC THIN DIP (P28-2, order code: TP) TOP VIEW PIN DESCRIPTIONS Symbol Name I/O Description D0 - D7 Data Inputs I Data inputs for a 8-bit bus. RS Reset I When RS is set LOW, internal read and write pointers are set to the first location of the RAM array, FF and AF go HIGH, and AE and EF go LOW. A reset is required before an initial WRITE after power-up. WCLK Write Clock I Data is written into the FIFO on a LOW-to-HIGH transition of WCLK when WEN is asserted. WEN Write Enable I When WEN is LOW, data is written into the FIFO on every LOW-to-HIGH transition of WCLK. Data will not be written into the FIFO if the FF is LOW. Q0 - Q7 Data Outputs O Data outputs for a 8-bit bus. RCLK Read Clock I Data is read from the FIFO on a LOW-to-HIGH transition of RCLK when REN is asserted. REN Read Enable I When REN is LOW, data is read from the FIFO on every LOW-to-HIGH transition of RCLK. Data will not be read from the FIFO if the EF is LOW. OE Output Enable I When OE is LOW, the data output bus is active. If OE is HIGH, the output data bus will be in a high-impedance state. EF Empty Flag O When EF is LOW, the FIFO is empty and further data reads from the output are inhibited. When EF is HIGH, the FIFO is not empty. EF is synchronized to RCLK. AE Almost-Empty Flag O When AE is LOW, the FIFO is almost empty based on the offset Empty+7. AE is synchronized to RCLK. AF Almost-Full Flag O When AF is LOW, the FIFO is almost full based on the offset Full-7. AF is synchronized to WCLK. FF Full Flag O When FF is LOW, the FIFO is full and further data writes into the input are inhibited. When FF is HIGH, the FIFO is not full. FF is synchronized to WCLK. VCC Power One +5 volt power supply pin. GND Ground One 0 volt ground pin. 2