TM 2.5 VOLT HIGH-SPEED TeraSync FIFO 36-BIT CONFIGURATIONS 65,536 x 36 IDT72T36105 131,072 x 36 IDT72T36115 262,144 x 36 IDT72T36125 FEATURES: User selectable input and output port bus-sizing Choose among the following memory organizations: - x36 in to x36 out IDT72T36105 65,536 x 36 - x36 in to x18 out - x36 in to x9 out IDT72T36115 131,072 x 36 - x18 in to x36 out IDT72T36125 262,144 x 36 - x9 in to x36 out Up to 225 MHz Operation of Clocks Big-Endian/Little-Endian user selectable byte representation User selectable HSTL/LVTTL Input and/or Output Auto power down minimizes standby power consumption 2.5V LVTTL or 1.8V, 1.5V HSTL Port Selectable Input/Ouput voltage Master Reset clears entire FIFO 3.3V Input tolerant Partial Reset clears data, but retains programmable settings Read Enable & Read Clock Echo outputs aid high speed operation Empty, Full and Half-Full flags signal FIFO status User selectable Asynchronous read and/or write port timing Select IDT Standard timing (using EF and FF flags) or First Word Mark & Retransmit, resets read pointer to user marked position Fall Through timing (using OR and IR flags) Write Chip Select (WCS) input enables/disables Write operations Output enable puts data outputs into high impedance state Read Chip Select (RCS) synchronous to RCLK JTAG port, provided for Boundary Scan function Programmable Almost-Empty and Almost-Full flags, each flag can Available in 240-pin (19mm x 19mm) Plastic Ball Grid Array (PBGA) Easily expandable in depth and width default to one of eight preselected offsets Independent Read and Write Clocks (permit reading and writing Program programmable flags by either serial or parallel means simultaneously) Selectable synchronous/asynchronous timing modes for Almost- High-performance submicron CMOS technology Empty and Almost-Full flags Industrial temperature range (40C to +85C) is available Separate SCLK input for Serial programming of flag offsets Green parts are available, see ordering information FUNCTIONAL BLOCK DIAGRAM D0 -Dn (x36, x18 or x9) LD SEN SCL K WEN WCL K/WR WCS INPUT REGISTER OF F SET REGISTER FF/IR PAF WRITE CONTROL ASYW EF/OR LOGIC FLAG PAE HF LOGIC RAM ARRAY FWFT/SI WRITE POINTER PFM 65,536 x 36 FSEL0 131,072 x36 FSEL1 262,144 x 36 BE CONTROL READ POINTER LOGIC IP BM BUS IW CONF IGURATION OW RT READ MARK CONTROL MRS OUTPUT REGISTER RESET ASYR LOGIC PRS LOGIC TCK TRST JTAG CONTROL RCL K/RD TMS (BOUNDARY SCAN) REN TDO RCS TDI Vr ef WHSTL HSTL I/0 EREN OE 5907 dr w01 RHSTL CONTROL SHSTL Q0 -Qn (x36, x18 or x9) ERCL K IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The TeraSync FIFO is a trademark of Integrated Device Technology, Inc. COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES JUNE 2017 1 DSC-5907/21IDT72T36105/115/125 2.5V TeraSync 36-BIT FIFO COMMERCIAL AND INDUSTRIAL 64K x 36, 128K x 36 and 256K x 36 TEMPERATURE RANGES PIN CONFIGURATION A1 BALL PAD CORNER A VCC VCC VCC VCC VCC VCC WCLK GND RCLK VDDQ VDDQ VDDQ VDDQ VDDQ PRS FF EREN OE B VCC VCC WEN VDDQ VDDQ VDDQ VDDQ VDDQ VCC VCC VCC VCC MRS GND PAF EF REN RCS C VCC VCC VCC VCC VCC VCC MARK VDDQ VDDQ VDDQ VDDQ VDDQ WCS LD GND HF PAE RT D VCC VCC VCC FWFT/SI OW FS0 SHSTL FS1 GND IP BM RHSTL PFM VDDQ VDDQ VDDQ BE ASYR E VCC VCC VCC GND GND VDDQ VDDQ VDDQ F VCC VCC VCC GND GND VDDQ VDDQ VDDQ G GND VDDQ VCC SCLK WHSTL VDDQ VDDQ SEN H VCC VCC VCC ASYW GND VDDQ VDDQ VDDQ GND GND GND GND J VCC VCC VCC VREF GND VDDQ VDDQ VDDQ GND GND GND GND K VCC VCC VCC IW GND VDDQ VDDQ VDDQ GND GND GND GND L D33 D34 D35 GND GND VDDQ Q35 Q34 GND GND GND GND M D32 GND Q32 D30 D31 GND Q33 Q31 N D27 GND Q29 D28 D29 GND Q30 Q28 P D24 D25 D26 GND GND Q27 Q26 Q25 R D22 GND GND GND GND D21 D23 GND GND GND GND GND GND GND GND Q24 Q23 Q22 T D19 D13 Q3 Q8 Q11 Q21 D20 D10 D5 D4 D1 TMS TDO GND Q0 Q2 Q14 Q20 U D18 D17 D14 D11 D7 D8 D2 TDI GND Q1 Q6 Q5 Q9 Q12 Q15 Q18 Q19 TRST V VCC D16 D15 D0 ERCLK Q4 Q7 Q10 Q13 Q17 VDDQ D12 D9 D6 D3 TCK GND Q16 12 34 56 7 8 9 10 11 12 13 14 15 16 17 18 5907 drw02A PBGA: 1mm pitch, 19mm x 19mm BB240, BBG240 (Order code: BB, BBG) TOP VIEW 2