CMOS SyncFIFO IDT72421, IDT72201 64 x 9, 256 x 9, 512 x 9, IDT72211, IDT72221 1,024 x 9, 2,048 x 9, IDT72231, IDT72241 4,096 x 9 and 8,192 x 9 IDT72251 LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018 FEATURES: DESCRIPTION: 64 x 9-bit organization (IDT72421) The IDT72421/72201/72211/72221/72231/72241/72251 SyncFIFO 256 x 9-bit organization (IDT72201) are very high-speed, low-power First-In, First-Out (FIFO) memories with 512 x 9-bit organization (IDT72211) clocked read and write controls. These devices have a 64, 256, 512, 1,024, 1,024 x 9-bit organization (IDT72221) 2,048, 4,096, and 8,192 x 9-bit memory array, respectively. These FIFOs are 2,048 x 9-bit organization (IDT72231) applicable for a wide variety of data buffering needs such as graphics, local area 4,096 x 9-bit organization (IDT72241) networks and interprocessor communication. 8,192 x 9-bit organization (IDT72251) These FIFOs have 9-bit input and output ports. The input port is controlled 10 ns read/write cycle time by a free-running clock (WCLK), and two write enable pins (WEN1, WEN2). Read and Write Clocks can be independent Data is written into the Synchronous FIFO on every rising clock edge when Dual-Ported zero fall-through time architecture the write enable pins are asserted. The output port is controlled by another clock Empty and Full Flags signal FIFO status pin (RCLK) and two read enable pins (REN1, REN2). The Read Clock can Programmable Almost-Empty and Almost-Full flags can be set be tied to the Write Clock for single clock operation or the two clocks can run to any depth asynchronous of one another for dual-clock operation. An output enable pin Programmable Almost-Empty and Almost-Full flags default to (OE) is provided on the read port for three-state control of the output. Empty+7, and Full-7, respectively The Synchronous FIFOs have two fixed flags, Empty (EF) and Full (FF). Output enable puts output data bus in high-impedance state Two programmable flags, Almost-Empty (PAE) and Almost-Full (PAF), are Advanced submicron CMOS technology provided for improved system control. The programmable flags default to Available in the 32-pin plastic leaded chip carrier (PLCC) and Empty+7 and Full-7 for PAE and PAF, respectively. The programmable flag 32-pin Thin Quad Flat Pack (TQFP) offset loading is controlled by a simple state machine and is initiated by asserting For through-hole product please see the IDT72420/72200/72210/ the load pin (LD). 72220/72230/72240 data sheet These FIFOs are fabricated using high-speed submicron CMOS technology. Industrial temperature range (40C to +85C) is available Green parts available, see ordering information FUNCTIONAL BLOCK DIAGRAM D0 - D8 WCLK LD WEN1 WEN2 OFFSET REGISTER INPUT REGISTER EF FLAG WRITE CONTROL PAE LOGIC LOGIC PAF FF RAM ARRAY 64 x 9, 256 x 9, 512 x 9, 1,024 x 9, WRITE POINTER READ POINTER 2,048 x 9, 4,096 x 9, 8,192 x 9 READ CONTROL LOGIC OUTPUT REGISTER RESET LOGIC RCLK REN1 REN2 RS 2655 drw01 OE Q0 - Q8 IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The SyncFIFO is a registered trademark of Integrated Device Technology, Inc. NOVEMBER 2017 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES 1 2017 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. DSC-2655/7IDT72421/72201/72211/72221/72231/72241/72251 CMOS SyncFIFO COMMERCIAL AND INDUSTRIAL 64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9 TEMPERATURE RANGES PIN CONFIGURATION INDEX INDEX 432 32 31 30 29 28 27 26 25 32 31 30 1 D1 29 RS 5 D1 1 24 D0 WEN1 6 28 WEN1 D0 2 23 WCLK 27 PAF 7 WCLK PAF 3 22 WEN2/LD 26 PAE 8 WEN2/LD 4 PAE 21 VCC 25 9 VCC GND GND 5 20 Q8 Q8 24 REN1 10 REN1 Q7 6 19 23 Q7 11 RCLK RCLK 7 18 Q6 22 Q6 REN2 12 REN2 17 8 Q5 21 Q5 OE 13 9 1011 12131415 16 14 15 16 17 18 19 20 2655 drw 02 2655 drw02a TQFP (PR32-1, order code: PF) PLCC (J32-1, order code: J) TOP VIEW TOP VIEW PIN DESCRIPTIONS Symbol Name I/O Description D0-D8 Data Inputs I Data inputs for a 9-bit bus. RS Reset I When RS is set LOW, internal read and write pointers are set to the first location of the RAM array,FF and PAF go HIGH, and PAE and EF go LOW. A reset is required before an initial WRITE after power-up. WCLK Write Clock I Data is written into the FIFO on a LOW-to-HIGH transition of WCLK when the Write Enable(s) are asserted. WEN1 Write Enable 1 I If the FIFO is configured to have programmable flags, WEN1 is the only write enable pin. When WEN1 is LOW, data is written into the FIFO on every LOW-to-HIGH transition WCLK. If the FIFO is configured to have two write enables, WEN1 must be LOW and WEN2 must be HIGH to write data into the FIFO. Data will not be written into the FIFO if the FF is LOW. WEN2/ Write Enable 2/ I The FIFO is configured at reset to have either two write enables or programmable flags. If WEN2/LD is HIGH LD Load at reset, this pin operates as a second write enable. If WEN2/LD is LOW at reset, this pin operates as a control to load and read the programmable flag offsets. If the FIFO is configured to have two write enables, WEN1 must be LOW and WEN2 must be HIGH to write data into the FIFO. Data will not be written into the FIFO if the FF is LOW. If the FIFO is configured to have programmable flags, WEN2/LD is held LOW to write or read the programmable flag offsets. Q0-Q8 Data Outputs O Data outputs for a 9-bit bus. RCLK Read Clock I Data is read from the FIFO on a LOW-to-HIGH transition of RCLK when REN1 and REN2 are asserted. REN1 Read Enable 1 I When REN1 and REN2 are LOW, data is read from the FIFO on every LOW-to-HIGH transition of RCLK. Data will not be read from the FIFO if the EF is LOW. REN2 Read Enable 2 I When REN1 and REN2 are LOW, data is read from the FIFO on every LOW-to-HIGH transition of RCLK. Data will not be read from the FIFO if the EF is LOW. OE Output Enable I When OE is LOW, the data output bus is active. If OE is HIGH, the output data bus will be in a high-impedance state. EF Empty Flag O When EF is LOW, the FIFO is empty and further data reads from the output are inhibited. When EF is HIGH, the FIFO is not empty. EF is synchronized to RCLK. PAE Programmable O When PAE is LOW, the FIFO is almost-empty based on the offset programmed into the FIFO. The default Almost-Empty Flag offset at reset is Empty+7. PAE is synchronized to RCLK. PAF Programmable O When PAF is LOW, the FIFO is almost-full based on the offset programmed into the FIFO. The default offset Almost-Full Flag at reset is Full-7. PAF is synchronized to WCLK. FF Full Flag O When FF is LOW, the FIFO is full and further data writes into the input are inhibited. When FF is HIGH, the FIFO is not full. FF is synchronized to WCLK. VCC Power One +5 volt power supply pin. GND Ground One 0 volt ground pin. 2 D2 OE EF D3 FF D4 Q0 D5 Q1 D6 Q2 D7 Q3 D8 Q4 RS D2 EF D3 FF D4 Q0 Q1 D5 Q2 D6 Q3 D7 Q4 D8