IDT72V801 3.3 VOLT DUAL CMOS SyncFIFO IDT72V811 IDT72V821 DUAL 256 X 9, DUAL 512 X 9, IDT72V831 DUAL 1,024 X 9, DUAL 2,048 X 9, IDT72V841 DUAL 4,096 X 9 , DUAL 8,192 X 9 IDT72V851 LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018 FEATURES: Each of the two FIFOs (designated FIFO A and FIFO B) contained in the The IDT72V801 is equivalent to two IDT72V201 256 x 9 FIFOs IDT72V801/72V811/72V821/72V831/72V841/72V851 has a 9-bit input data The IDT72V811 is equivalent to two IDT72V211 512 x 9 FIFOs port (DA0 - DA8, DB0 - DB8) and a 9-bit output data port (QA0 - QA8, The IDT72V821 is equivalent to two IDT72V221 1,024 x 9 FIFOs QB0 - QB8). Each input port is controlled by a free-running clock (WCLKA, The IDT72V831 is equivalent to two IDT72V231 2,048 x 9 FIFOs WCLKB), and two Write Enable pins (WENA1, WENA2, WENB1, WENB2). The IDT72V841 is equivalent to two IDT72V241 4,096 x 9 FIFOs Data is written into each of the two arrays on every rising clock edge of the Write The IDT72V851 is equivalent to two IDT72V251 8,192 x 9 FIFOs Clock (WCLKA, WCLKB) when the appropriate Write Enable pins are Offers optimal combination of large capacity, high speed, asserted. design flexibility and small footprint The output port of each FIFO bank is controlled by its associated clock pin Ideal for prioritization, bidirectional, and width expansion (RCLKA, RCLKB) and two Read Enable pins (RENA1, RENA2, RENB1, applications RENB2). The Read Clock can be tied to the Write Clock for single clock operation 10 ns read/write cycle time or the two clocks can run asynchronous of one another for dual clock operation. 5V input tolerant An Output Enable pin (OEA, OEB) is provided on the read port of each FIFO Separate control lines and data lines for each FIFO for three-state output control. Separate Empty, Full, programmable Almost-Empty and Each of the two FIFOs has two fixed flags, Empty (EFA, EFB) and Full (FFA, Almost-Full flags for each FIFO FFB). Two programmable flags, Almost-Empty (PAEA, PAEB) and Almost-Full Enable puts output data lines in high-impedance state (PAFA, PAFB), are provided for each FIFO bank to improve memory utilization. Space-saving 64-pin plastic Thin Quad Flat Pack (TQFP/ If not programmed, the programmable flags default to Empty+7 for PAEA and STQFP) PAEB, and Full-7 for PAFA and PAFB. Industrial temperature range (40C to +85C) is available The IDT72V801/72V811/72V821/72V831/72V841/72V851 architecture Green parts available, see ordering information lends itself to many flexible configurations such as: 2-level priority data buffering DESCRIPTION: Bidirectional operation Width expansion The IDT72V801/72V811/72V821/72V831/72V841/72V851/72V851 are Depth expansion dual synchronous (clocked) FIFOs. The device is functionally equivalent to This FIFO is fabricated using IDT s high-performance submicron CMOS two IDT72V201/72V211/72V221/72V231/72V241/72V251 FIFOs in a single technology. package with all associated control, data, and flag lines assigned to separate pins. FUNCTIONAL BLOCK DIAGRAM EFA WCLKB WCLKA PAEA WENB1 WENA1 DA0 - DA8 DB0 - DB8 PAFA LDA LDB WENA2 WENB2 FFA INPUT REGISTER OFFSET REGISTER INPUT REGISTER OFFSET REGISTER EFB FLAG WRITE CONTROL FLAG WRITE CONTROL PAEB LOGIC LOGIC LOGIC LOGIC PAFB FFB RAM ARRAY RAM ARRAY 256 x 9, 512 x 9, 256 x 9, 512 x 9, WRITE POINTER READ POINTER WRITE POINTER READ POINTER 1,024 x 9, 2,048 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9, 8,192 x 9 4,096 x 9, 8,192 x 9 READ CONTROL READ CONTROL LOGIC LOGIC OUTPUT REGISTER OUTPUT REGISTER RESET LOGIC RESET LOGIC 4093 drw 01 RCLKB RSA OEA RCLKA RSB OEB RENB1 QB0 - QB8 QA0 - QA8 RENB2 RENA1 RENA2 IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The TeraSync FIFO is a trademark of Integrated Device Technology, Inc. COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES MARCH 2018 1 2018 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. DSC-4093/6TM IDT72V801/72V8211/72V821/72V831/72V841/72V851 3.3V DUAL CMOS SyncFIFO COMMERCIAL AND INDUSTRIAL DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9 TEMPERATURE RANGES PIN CONFIGURATION QB0 1 48 QA1 FFB 2 47 QA2 EFB 3 46 QA3 OEB 4 45 QA4 RENB2 5 44 QA5 RCLKB 6 43 QA6 RENB1 7 42 QA7 GND 8 41 QA8 9 40 Vcc VCC 10 39 PAEB WENA2/LDA 11 38 PAFB WCLKA 12 37 DB0 WENA1 13 36 DB1 RSA 14 35 DB2 DA8 15 34 DB3 DA7 16 33 DB4 DA6 4093 drw 02 TQFP (PN64, order code: PF) STQFP (PP64, order code: TF) TOP VIEW 2 DA5 17 64 QA0 DA4 18 63 FFA EFA 19 62 DA3 OEA 20 61 DA2 21 60 RENA2 DA1 22 59 RCLKA DA0 PAFA 23 58 RENA1 GND PAEA 24 57 25 56 QB8 WENB2/LDB 26 55 QB7 WCLKB 27 54 QB6 WENB1 28 53 QB5 RSB 29 52 QB4 DB8 30 51 QB3 DB7 31 50 QB2 DB6 32 49 QB1 DB5