3.3 VOLT CMOS SuperSync FIFO 65,536 x 9 IDT72V281 131,072 x 9 IDT72V291 LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018 Independent Read and Write clocks (permit reading and writing FEATURES: simultaneously) Choose among the following memory organizations: Available in the 64-pin Thin Quad Flat Pack (TQFP) and the 64-pin IDT72V281 65,536 x 9 Slim Thin Quad Flat Pack (STQFP) IDT72V291 131,072 x 9 High-performance submicron CMOS technology Pin-compatible with the IDT72V261/72V271 SuperSync FIFOs Industrial Temperature Range (-40C to + 85C) is available 10ns read/write cycle time (6.5ns access time) Green parts available, see ordering information Fixed, low first word data latency time Auto power down minimizes standby power consumption DESCRIPTION: Master Reset clears entire FIFO Partial Reset clears data, but retains programmable The IDT72V281/72V291 are exceptionally deep, high speed, CMOS settings First-In-First-Out (FIFO) memories with clocked read and write controls. Retransmit operation with fixed, low first word data These FIFOs offer numerous improvements over previous SuperSync latency time FIFOs, including the following: Empty, Full and Half-Full flags signal FIFO status The limitation of the frequency of one clock input with respect to the other has Programmable Almost-Empty and Almost-Full flags, each flag can been removed. The Frequency Select pin (FS) has been removed, thus default to one of two preselected offsets it is no longer necessary to select which of the two clock inputs, RCLK or Program partial flags by either serial or parallel means WCLK, is running at the higher frequency. Select IDT Standard timing (using EFEFEFEFEF and FFFFFFFFFF flags) or First Word The period required by the retransmit operation is now fixed and short. Fall Through timing (using OROROROROR and IRIRIRIRIR flags) The first word data latency period, from the time the first word is written to an Output enable puts data outputs into high impedance state empty FIFO to the time it can be read, is now fixed and short. (The variable Easily expandable in depth and width clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated on this SuperSync family.) FUNCTIONAL BLOCK DIAGRAM D0-D8 WEN WCLK LD SEN INPUT REGISTER OFFSET REGISTER FF/IR PAF FLAG EF/OR WRITE CONTROL LOGIC PAE LOGIC HF FWFT/SI RAM ARRAY 65,536 x 9 131,072 x 9 WRITE POINTER READ POINTER READ RT CONTROL LOGIC OUTPUT REGISTER MRS RESET RCLK LOGIC PRS REN Q0-Q8 4513 drw 01 OE IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The SuperSync FIFO is a trademark of Integrated Device Technology, Inc. COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES JANUARY 2018 1 DSC-4513/5 2018 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.TM IDT72V281/72V291 3.3V CMOS SUPERSYNC FIFO COMMERCIAL AND INDUSTRIAL 65,536 x 9 and 131,072 x 9 TEMPERATURE RANGES The frequencies of both the RCLK and the WCLK signals may vary from 0 DESCRIPTION (Continued) to fMAX with complete independence. There are no restrictions on the frequency SuperSync FIFOs are particularly appropriate for network, video, telecommu- of the one clock input with respect to the other. nications, data communications and other applications that need to buffer large There are two possible timing modes of operation with these devices: amounts of data. IDT Standard mode and First Word Fall Through (FWFT) mode. The input port is controlled by a Write Clock (WCLK) input and a Write In IDT Standard mode, the first word written to an empty FIFO will not Enable (WEN) input. Data is written into the FIFO on every rising edge of appear on the data output lines unless a specific read operation is WCLK when WEN is asserted. The output port is controlled by a Read performed. A read operation, which consists of activating REN and Clock (RCLK) input and Read Enable (REN) input. Data is read from the enabling a rising RCLK edge, will shift the word from internal memory to the FIFO on every rising edge of RCLK when REN is asserted. An Output data output lines. Enable (OE) input is provided for three-state control of the outputs. PIN CONFIGURATIONS PIN 1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 (3) 1 48 DNC WEN (3) SEN 2 47 DNC (1) DC 3 46 GND (3) VCC 4 45 DNC (3) DNC VCC 5 44 (2) 43 VCC GND 6 (3) (2) DNC GND 7 42 (3) (2) GND 8 41 DNC (2) (3) GND DNC 9 40 (2) GND 10 39 GND (2) (3) DNC GND 11 38 (2) (3) DNC GND 12 37 (2) GND Q8 13 36 (2) GND Q7 14 35 D8 Q6 15 34 D7 GND 16 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 4513 drw 02 TQFP (PN64, order code: PF) STQFP (PP64, order code: TF) TOP VIEW NOTES: 1. DC = Dont Care. Must be tied to GND or VCC, cannot be left open. 2. This pin may either be tied to ground or left open. 3. DNC = Do Not Connect. 2 WCLK PRS D5 MRS D4 D3 LD D2 FWFT/SI D1 GND D0 FF/IR GND PAF Q0 HF VCC Q1 PAE GND Q2 EF/OR RCLK Q3 VCC REN Q4 RT Q5 OE D6